Method of forming semiconductor device

Abstract

The present disclosure discloses a method of forming a semiconductor device. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a layer of material on a plurality of sidewalls of the mandrel; implanting a dopant into the material layer Middle; performing an etch process on the hard mask layer using the mandrel and material layer as an etch mask to form a patterned hard mask layer, wherein the etch process simultaneously produces multiple sidewalls deposited on the patterned hard mask layer a dielectric layer containing a dopant; and forming fins by etching the substrate using the patterned hard mask layer and the dielectric layer together as an etch mask.

Description

technical field [0001] Embodiments of the invention relate to a method for forming a semiconductor device. Background technique [0002] The semiconductor integrated circuit (integrated circuit, IC) industry has experienced exponential development. Technological advances in the materials and design of integrated circuits have produced generations of integrated circuits, with each generation having smaller and more complex circuits than the previous generation. During the development of integrated circuits, functional density (ie, the number of interconnected devices per die area) generally increases while geometry size (ie, the smallest component (or line) that can be fabricated with a manufacturing process) decreases. This downsizing process often provides benefits through increased production efficiency and reduced associated costs. This shrinkage also increases the complexity of handling and manufacturing integrated circuits. [0003] For example, multi-gate devices ha...

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Problems solved by technology

However, controlling the fin width during fin patterning is daunting

For example, fins with different material compositions suffer from different lateral losses during fabrication, resulting in inconsistent fin widths between N-type FinFETs and P-type FinFETs

Thus, while conventional fin patterning methods have generally served their intended purpose, they have not been satisfactory in all respects

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