Semiconductor device including pg alignment unit and method of generating layout thereof

Abstract

The semiconductor structure includes a power grid layer (including a first metallization layer) and a group of cells. The first metallization layer includes: a conductive first portion and a conductive second portion providing respective supply voltages and reference voltages and having respective long axes oriented substantially parallel to the first direction; and a conductive third portion and a conductive first portion Four sections providing respective supply voltages and reference voltages and having respective major axes oriented substantially parallel to a second direction, wherein the second direction is substantially perpendicular to the first direction. Cell groups are located below the PG layer. Each cell lacks the conductive structures included in the first metallization layer. The cells are arranged in repeating relationship relative to at least one of the first and second portions of the first metallization layer to overlap at least one of the first and second portions. Embodiments of the present invention also relate to semiconductor devices including PG alignment cells and methods of generating layouts thereof.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor devices including PG alignment cells and methods of generating layouts thereof. Background technique [0002] One method used to represent semiconductor devices is a plan view known as a layout diagram. During the placement phase in which the layout diagram is generated, the rows in the layout diagram are populated with standard functional cells from a library of various standard cell configurations. Depending on the design, number of layers, etc., the area utilization of standard functional cells is limited to, for example, about 80% or less in order to leave room for signal routing. If the area utilization of functional standard cells exceeds about 80%, routability is significantly reduced, and noise distribution is significantly deteriorated, resulting in timing failure and the like. Contents of the invention [0003] Embodiments of the present invention provide a semiconductor structu...

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Problems solved by technology

If the area utilization of the functional standard cell exceeds about 80%, the routability is significantly reduced, and the noise distribution is significantly deteriorated, resulting in timing failure, etc.

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