Physical coding circuit and high speed interface protocol switch chip

Abstract

The invention provides a physical coding circuit and a high speed interface protocol switch chip. The physical coding circuit includes a general logic module, a configurable logic module and a configuration register. The general logic module includes a plurality of general sub-circuits. The configurable logic module includes a plurality of configurable sub-modules. The configurable sub-module includes a plurality of configurable sub-circuits and selectors. The configuration register receives a configuration instruction sent by a software definition control circuit, and sets the parameters of the general logic module according to the configuration instruction, and activates the corresponding configurable sub-circuit through the selector. The general logic module and the activated configurable sub-circuit encode the to-be-encoded data sent by the software definition control circuit according to a high speed interface protocol corresponding to the configuration instruction to obtain the encoded data, and send the encoded data to a physical medium transmission circuit. The physical coding circuit and the high speed interface protocol switch chip improves the multiplexing degree of physical coding circuits, thereby reducing parameters such as volume and weight of high speed interface protocol switch chips.

Description

technical field [0001] The invention relates to the technical field of high-speed interface protocols, in particular to a physical coding circuit and a high-speed interface protocol switching chip. Background technique [0002] At present, the physical coding circuit (also known as physical coding sub-layer, PCS, Physical Coding Sub-layer) design in the existing high-speed interface protocol switching chip is mainly divided into two types, one is because the chip itself only supports one high-speed Interface protocol, so only a single PCS layer design is used internally; the other is that although the chip supports more than one high-speed interface protocol, the circuit design between different protocols is completely independent, so multiple completely independent PCS circuits are designed internally according to the type of protocol. [0003] The PCS circuit design of a single protocol cannot meet the interactive processing requirements of the switching chip for different...

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Problems solved by technology

[0003] The PCS circuit design of a single protocol cannot meet the interactive processing requirements of the switching chip for different types of protocols; while the multi-protocol independent PCS circuit design solves the problem of multi-protocol switching, but due to the independent design of each PCS layer, the circuit design has a low degree of reuse , leading to an increase in the area and power consumption of the switching chip itself, which directly affects the volume, weight, power consumption and other indicators of the system

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