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A verification method and verification device

A verification method and verification device technology, applied in the field of verification methods and verification devices, can solve the problems affecting the efficiency of CNN design, low comparison efficiency, and long time spent, so as to avoid layer-by-layer comparison and improve verification efficiency Effect

Active Publication Date: 2021-07-09
深兰人工智能芯片研究院(江苏)有限公司
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  • Claims
  • Application Information

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Problems solved by technology

[0004] At present, the comparison between the running results of the FPGA design and the simulation results is done manually, which takes a long time and the comparison efficiency is low, especially when the neural network has many layers, and each layer of the neural network has calculated data. case, but will affect the efficiency of FPGA-based CNN design

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Embodiment Construction

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0035] At present, the comparison between the running results of the FPGA design and the simulation results is done manually, which takes a long time and the comparison efficiency is low, especially when the neural network has many layers, and each layer of the neural network has calculated data. In this case, it will affect the efficiency of FPGA-based CNN design.

[0036] In view of this, the embodiment of the present application provides a verification method. The host side obtains the running result of the currently running neural network layer from the FPGA board, and performs the running result according to the simulation result of the computer software s...

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Abstract

The application discloses a verification method and a verification device, which are used to improve the verification efficiency of operation results. Among them, the verification method includes: when the field programmable array FPGA board is accelerated to realize the convolutional neural network, the upper computer software sequentially enables the convolutional neural network layer through the first self-defined register, and automatically detects when the corresponding layer operation result ends, Obtain the operation results of the current layer of the convolutional neural network through the PCIE interface; compare with the simulation results of the computer software simulation corresponding to the neural network layer, if the comparison results are consistent, automatically enable the next layer of network to continue operation, if the comparison is inconsistent, the returned results are inconsistent network operating layer and location information.

Description

technical field [0001] The present application relates to the technical field of neural network hardware acceleration, and in particular to a verification method and a verification device. Background technique [0002] With the rapid development of artificial intelligence, neural networks are getting more and more attention. At present, most of the neural networks are implemented by software, which requires a large amount of data and requires high computing power of the hardware. It relies on the high computing power of the cloud and consumes a lot of power. [0003] In view of the above problems, the use of a field-programmable gate array (Field-Programmable Gate Array, FPGA) accelerator to implement a convolutional neural network (Convolutional Neural Network, CNN) has gradually been proposed. The implementation process is to use FPGA to accelerate the convolutional neural network after designing and simulating with computer software. When designing CNN with FPGA, various...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/26
CPCG06F11/261
Inventor 陈海波
Owner 深兰人工智能芯片研究院(江苏)有限公司