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A method of testing RAM

A technology to be tested and consistent, applied in the field of testing RAM, can solve the problems of incomplete SDRAM testing, insufficient testing data, and reducing test reliability, etc., to achieve the effect of wide application range, comprehensive testing, and improved reliability

Inactive Publication Date: 2019-03-29
XIAN INTELLIGENCE SILICON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the above-mentioned method for testing SDRAM devices, the test data is not sufficient, and the same data (all 1 or all 0) will be written in the Full Page mode mentioned in test step b, which will cause the test data to be too one-sided. If there is a problem with a certain address line, writing the same data will cover up the error, thereby reducing the reliability of the test; in addition, although the above method of testing SDRAM devices uses multiple clock signals in the test, the highest frequency clock signal is also Slightly low, resulting in an incomplete test based on SDRAM, only for the function of SDRAM, not related to the performance test of SDRAM

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  • A method of testing RAM

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Embodiment 1

[0038] See figure 1 , figure 1 A schematic flow chart of a method for testing RAM provided by an embodiment of the present invention, including the following steps:

[0039] Step S1, initial setting: firstly power on the RAM to be tested; then perform initial setting.

[0040] Specifically, the initialization setting includes setting an initial address value of the RAM to be tested, etc., for example, setting the initial address value of the RAM to be tested to 0.

[0041] Step S2, write: write the first data in the address unit of the RAM to be tested until the address unit is full; specifically, first generate the first data according to the bit width of the RAM, and then start from the first address of the RAM to be tested Initially, the first data is sequentially written into the address units of the RAM until the address units of the RAM are full; specifically, the first address at which the first data is written is 0.

[0042] In one embodiment of the present inventio...

Embodiment 2

[0058] See figure 2 , figure 2 A schematic flow chart of another method for testing RAM provided by an embodiment of the present invention, including steps:

[0059] S1. Initialization setting: first power on the RAM to be tested; then perform initialization setting.

[0060] Specifically, the initialization setting includes setting an initial address value of the RAM to be tested, etc., for example, setting the initial address value of the RAM to be tested to 0.

[0061] S2, write: write the first data in the address unit of the RAM to be tested; specifically, first generate the first data according to the bit width of the RAM, and then write the first data into the address unit of the RAM to be tested; specifically, The first address for starting to write the first data may be 0.

[0062] In an embodiment of the present invention, the first data includes a random number; specifically, the random number is generated according to the bit width of the RAM to be tested, and...

Embodiment 3

[0077] In one embodiment of the present invention, the test method of embodiment 1 and embodiment 2 can be used to determine whether the RAM is intact and reliable, and can test the performance of RAM. The test method of embodiment 2 is taken as an example for illustration. Please refer to figure 2 .

[0078] When judging whether the RAM is in good condition, the test clock frequency is 0-100MHz. The test process is as follows: firstly, the RAM to be tested is powered on, and the initial value of the address of the RAM to be tested is set to 0; Number, control the random number to be written into one of the address units of the RAM to be tested; read the random number in the RAM address unit to obtain the second data corresponding to the random number; check the random number and the second data to obtain two Two verification data: the first verification data and the second verification data; compare the two verification data to judge whether the two verification data are con...

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Abstract

The invention relates to a method for testing a RAM, comprising the steps of: writing first data into an address unit of a RAM to be tested, wherein, the first data comprises a random number; readingthe address unit to obtain second data; verifying the first data and the second data to obtain the first verification data and the second verification data, respectively; comparing whether the first check data and the second check data coincide. A method for testing RAM of that embodiment of the invention avoids the problem that the test data is too one-sided by adopting random numbers to test RAM, and has high test coverage rate, so that errors in the RAM can be fully detected, the RAM to be tested is more effectively detected, and the reliability of the test is improved.

Description

technical field [0001] The invention belongs to the technical field of memory testing, and in particular relates to a method for testing RAM. Background technique [0002] Random access memory (random access memory, RAM), also known as "random access memory", is an internal memory that directly exchanges data with the CPU, and is also called main memory (memory). It can be read and written at any time, and the speed is very fast, and it is usually used as a temporary data storage medium for operating systems or other running programs. When using these RAMs, it is necessary to judge the RAM in advance to ensure that the RAM can work normally. [0003] Patent CN100343923C introduces a method for testing SDRAM devices, including the following steps: a. setting the working mode of SDRAM to be tested as Full Page mode; b. activating the address lines and control lines of SDRAM to be tested that need to be accessed, and transferring test data Write to the corresponding storage u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/18G11C29/36G11C29/42
CPCG11C29/18G11C29/36G11C29/42
Inventor 尹文芹段媛媛贾红程显志陈维新韦嶔
Owner XIAN INTELLIGENCE SILICON TECH INC