Drive circuit
A technology for driving circuits and circuits, applied in logic circuits, logic circuit connection/interface layout, electronic switches, etc., can solve the problem that high-end transistors cannot stably output high-voltage side output signals.
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[0015] Embodiments will be described below with reference to the drawings.
[0016] figure 1 It is a circuit diagram of an example of the driving circuit 1 according to the embodiment. figure 2 is a circuit diagram of an example of the reference voltage circuit 42 according to the embodiment. image 3 It is a circuit diagram of an example of an inversion buffer B1 of the drive circuit 1 according to the embodiment. Figure 4 It is a circuit diagram of an example of an inversion buffer B2 of the drive circuit 1 according to the embodiment.
[0017] Such as figure 1 As shown, the dead time generator 2 is connected to the input terminal Vin, the high voltage side circuit 3 and the low voltage side circuit 4 . The high-voltage side circuit 3 and the low-voltage side circuit 4 are connected to the output terminal Vout. A load device is connected to the output terminal Vout.
[0018] The input signal input to the input terminal Vin is, for example, a PWM signal. The input si...
example 2
[0085] In the embodiment and Modification 1 of the embodiment, the level shift circuit 21 is connected in series to the level shift circuit 11 , but the level shift circuit 21 a may be connected in parallel to the level shift circuit 11 .
[0086] Image 6 It is a circuit diagram of an example of a drive circuit 1b according to Modification 2 of the embodiment. In this modified example, description of the same configuration as other modified examples is omitted.
[0087] The drive circuit 1b has a level shift circuit 21a and a timing adjustment circuit 31b.
[0088] The level shift circuit 21a is connected to the dead time generator 2 in parallel with the level shift circuit 11, so as to be input with the high-voltage side drive signal, and shift the high-voltage side drive signal to a predetermined second signal level to generate a switch The signal S2 is output to the timing adjustment circuit 31b.
[0089] The switching signal S2 is delayed from the switching signal S1 b...
example 3
[0095] In Modification 1 of the embodiment, the drive circuit 1a has a switch unit Sw2a, and in Modification 2 of the embodiment, the drive circuit 1b has a level shift circuit 21a and a timing adjustment circuit 31b, but the drive circuit 1c may also have a switch unit. Sw2a, the level shift circuit 21a, and the timing adjustment circuit 31c.
[0096] Figure 7 It is a circuit diagram of an example of a drive circuit 1c according to Modification 3 of the embodiment. In this modified example, description of the same configuration as other modified examples is omitted.
[0097] Such as Figure 7 As shown, the drive circuit 1c has the switch part Sw2a, the level shift circuit 21a, and the timing adjustment circuit 31c.
[0098] The timing adjustment circuit 31c is connected to the pre-driver 51 via the inversion buffer B2. The timing adjustment circuit 31c delays the switching signal S2 input from the level shift circuit 21a by a predetermined sixth time and outputs it to th...
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