SiP system based on JTAG test and JTAG test method of inside chip of SiP system
A test method and technology of the chip under test, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of high test plan planning efficiency, complex testing, and various types of functional tests in SiP modules, so as to improve accessibility. , the effect of improving controllability
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[0026] The present invention will be described in detail below with reference to the drawings and embodiments.
[0027] The present invention proposes a JTAG test method for SiP system based on JTAG test and its internal chip. This method is aimed at the characteristic that the chip in the SiP module is completely enclosed or semi-completely enclosed in the system package. The internal chip of the SiP module is designed through the interconnection design of the chip embedded in the SiP module, and the chip's boundary scan unit and JTAG test port are used. Realize the data path.
[0028] The SiP system based on JTAG test includes a JTAG test access port, at least two chips compliant with the JTAG protocol, which are marked as the first JTAG chip and the last JTAG chip. The test input terminal TDI of the JTAG test access port is connected to the JTAG test input of the first JTAG chip On the terminal TDI, the first JTAG chip JTAG test output terminal TDO is connected to the last JTAG...
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