Reduced instruction set processor based on a memristor
A technology that simplifies instruction sets and processors, and is applied in instruction analysis, electrical digital data processing, instruments, etc., to achieve the effect of saving power consumption and shortening processing time
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Embodiment 1
[0080] The operation sequence of embodiment 1 is as follows, all bit line switches and connection switches are defaulted to off state before the operation starts:
[0081] (1.1) The row selection module selects the 6 CMUs with corresponding addresses respectively, and sets their selected bits p to 1.
[0082] (1.2) Carry out a round of marking position setting:
[0083]
[0084]
[0085] (1.3) The connection switch connects A1 and A2 according to the values of connection bits c1 and c2, connects A3 and A4, and A5 and A6 are not connected with any unit; the column selection module cooperates with the row selection module to close the 11-0 bits of A1 and A2 Bit line switches, close all 32 bit line switches of A3 and A4, and close the 31st to 16th bit line switches of A5.
[0086] (1.4) After the voltage application module finds all units with p=1, it applies the voltage V to A1 and A3 according to the values of the voltage judgment bits v1 and v2 COND , apply voltage...
Embodiment 2
[0106] The operation sequence of embodiment 2 is as follows, all bit line switches and connection switches are defaulted to off state before the operation starts:
[0107] (2.1) The row selection module selects the CMU whose on-chip address is 0x31D according to the value in the program counter (for convenience of description, it is recorded as unit A), the auxiliary unit MOV1 of the data movement auxiliary block in the auxiliary area, and the address of the instruction cache 0x000 ( For the convenience of description, it is recorded as unit I), and their selected bits p are all set to 1.
[0108] (2.2) Carry out a round of marking position setting:
[0109] CMU
c1
c2
v1
v2
A
0
0
1
1
MOV1
0
0
0
0
I
0
0
0
0
[0110] (2.3) The column selection module cooperates with the row selection module to close all 32 bit line switches of MOV1 and I.
[0111] (2.4) The voltage application module applies volta...
example 2
[0121] The instruction fetching stage shown in Example 2 is not only an operation step of data movement, but also an operation step of the instruction fetching stage of all instructions.
[0122] From Example 1 and Example 2, in addition to the initial address generation, selection, and final deselection, a (or concurrent) implication / clearing / setting operation will go through the following steps: mark position setting→closing Make / Bit Line Switch → Apply Voltage to Include / Clear / Set → Open Make / Bit Line Switch. In the subsequent instruction execution examples, the control steps such as setting the mark position, closing the bit line / connection switch, and disconnecting the bit line / connection switch are omitted, and only the initial address generation, selection, and completion of the command function are given. Elapsed imply / clear / set operations, and finally deselect operations.
[0123] After the instruction fetching stage, enter the instruction decoding and execution stag...
PUM
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