Multi-chip simultaneous measurement structure and method

Abstract

The invention discloses a multi-chip simultaneous testing structure, which conducts electrical testing on chips on a wafer. The chips to be tested on the wafer are divided into rows and columns to form a test array, and the chips to be tested on the same column are connected in parallel. Form the test port of each column; The test port is connected to the power channel of the tester; The chips to be tested on the same row share a control switch; The tester has a plurality of power channels, and one tester power channel corresponds to a column of the tester The test port of the chip. The invention also discloses a simultaneous testing method of the multi-chip simultaneous testing structure. By reasonably matching the chips to be tested with the channels of the tester, the number of simultaneous tests is increased, and the power consumption of each chip to be tested is realized. Parametric test, the test unit that encounters a short circuit during the test can be isolated through the corresponding control switch, reducing misjudgment.

Description

technical field [0001] The invention relates to the field of manufacturing and testing of semiconductor integrated circuits, in particular to a method for simultaneously testing a plurality of chips (die) on a wafer. Background technique [0002] Chip testing is the measurement of electrical parameters on silicon wafer-level integrated circuits for the purpose of verifying acceptable electrical performance. The electrical specifications used during testing vary with the purpose of the test. [0003] In the semiconductor chip testing industry, with the continuous advancement of technology, the process size is getting smaller and smaller, and the chip area is getting smaller and smaller. In other words, the number of chips (die) on the same size wafer is increasing . For wafer testing, due to the increase in the number of chips, if the same test number remains unchanged, the test efficiency will inevitably decrease. Since the testing process does not increase the value of t...

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Problems solved by technology

[0005] In this way, although the number of simultaneous measurements has been increased, the disadvantages it brings are also obvious

First of all, due to the parallel structure, the test result is that the power consumption parameters of a single DUT cannot be tested, and only the total power consumption of a group of DUTs connected in parallel can be obtained; secondly, when these DUTs in a group of DUTs sharing a DPS resource channel When a DUT or some DUTs are short-circuited to the ground, the power of the entire group of DUTs can only be turned off, and all DUTs are set as invalid DUTs, so there is a situation of overkill, and in the periphery of the wafer, this situation will become obvious

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