Method for manufacturing semiconductor device isolation sidewall
A device isolation and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting device performance, size offset, and plasma plasma directionality, etc., to improve device performance and improve uniformity effect
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no. 1 example
[0041] The first embodiment of the semiconductor device isolation sidewall manufacturing method provided by the present invention, taking 2X NAND as an example, includes the following steps:
[0042] 1) if figure 1 As shown, make a semiconductor isolation sidewall spacer;
[0043] 2) if figure 2 As shown, make a sacrificial layer to cover the spacer of the isolation side wall;
[0044] 3) if image 3 As shown, the first sacrificial layer etching is performed to remove part of the sacrificial layer, and the first sacrificial layer etching etches the sacrificial layer to the starting position of the asymmetric morphology of the isolation sidewall;
[0045] 4) if Figure 4 As shown, the isolation side wall spacer is formed by etching the isolation side wall, and the design profile is a square isolation side wall graphic appearance;
[0046] 5) if Figure 5 As shown, a second sacrificial layer etch was performed to remove all the sacrificial layer.
no. 2 example
[0047] The second embodiment of the semiconductor device isolation sidewall manufacturing method provided by the present invention, taking 2X NAND as an example, includes the following steps:
[0048] 1) if figure 1 As shown, make a semiconductor isolation sidewall spacer;
[0049] 2) if figure 2 As shown, a sacrificial layer is made to cover the isolation spacer, and the sacrificial layer is an organic dielectric layer or a carbon-coated square pet;
[0050] 3) if image 3 As shown, the first sacrificial layer etching is performed to remove part of the sacrificial layer, and the first sacrificial layer etching etches the sacrificial layer to the starting position of the asymmetric morphology of the isolation sidewall;
[0051] 4) if Figure 4 As shown, the isolation side wall spacer is formed by etching the isolation side wall to form a designed shape, and the designed shape is a square isolation side wall graphic shape;
[0052] 5) if Figure 5 As shown, a second sacr...
no. 3 example
[0053]The third embodiment of the semiconductor device isolation sidewall manufacturing method provided by the present invention, taking 2X NAND as an example, includes the following steps:
[0054] 1) if figure 1 As shown, make a semiconductor isolation sidewall spacer;
[0055] 2) if figure 2 As shown, a sacrificial layer is made to cover the isolation spacer, and the sacrificial layer is an organic dielectric layer or a carbon-coated square pet;
[0056] 3) if image 3 As shown, the first sacrificial layer etching is performed to remove part of the sacrificial layer, and the first sacrificial layer etching adopts dry etching, and the first sacrificial layer etching etches the sacrificial layer to the isolation spacer wall The starting position of the symmetrical shape;
[0057] 4) if Figure 4 As shown, the spacer is etched to form the spacer with the designed shape, and the designed shape is a square spacer pattern; the spacer is etched on the spacer above the remain...
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