Novel 3D NAND memory device and method of forming same

Abstract

A 3D NAND memory device is provided and includes: a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines disposed above the BSG and having a stepped configuration, and a plurality of insulation layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend along the length of the substrate to separate the BSG into a plurality of sub-BSGs. Further, one or more common source regions are formed over the substrate and extend in the lengthdirection of the substrate. One or more common source regions also extend through the BSG, the plurality of word lines, and the plurality of insulating layers.

Description

Background technique [0001] As feature sizes of devices in integrated circuits shrink to the limits of common memory cell technology, designers have sought techniques for stacking multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit. [0002] 3D-NAND memory devices are exemplary devices that stack multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit. 3D-NAND technology is moving towards high density and high capacity, especially from 64L to 128L architecture, and the number of word line layers (or gate control layers) in the vertical direction perpendicular to the substrate has increased significantly. The increase in the number of word line layers leads to a significant increase in the block size of 3D-NAND memory devices, which in turn leads to longer read and erase times, longer data transfer times, and lower storage efficiency. Contents of the invention [0003] The inventive con...

AI Technical Summary

Problems solved by technology

The increase in the number of word line layers leads to a significant increase in the block size of 3D-NAND memory devices, which in turn leads to longer read and erase times, longer data transfer times, and lower storage efficiency

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