Clock frequency division method, device and system, system-on-chip and storage medium

Abstract

The invention is applicable to the technical field of electronics, and provides a clock frequency division method, device and system, a system-on-chip and a storage medium, and the method comprises the steps: starting to count the number of clock periods of a clock signal sent by an external clock source if a power-on stable signal sent by the system-on-chip is received; If a system initializationcompletion signal sent by the system-on-chip is received, stopping counting the number of clock periods of a clock signal sent by an external clock source; Counting a counting result of counting thenumber of clock periods of the clock signal sent by the external clock source, and obtaining a corresponding frequency division coefficient according to the counting result; And performing frequency division processing on the frequency of the clock signal sent by the external clock source according to the frequency division coefficient, and outputting the clock signal subjected to the frequency division processing to the phase-locked loop. The clock frequency division method does not need to modify a system-on-chip program, and is high in working efficiency, high in application development efficiency, wide in application range and low in process complexity.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a clock frequency division method, device, system, system on chip and storage medium. Background technique [0002] With the development of integrated circuits, a system on chip (System on Chip, SOC) emerges as the times require. Because the system-on-chip needs a clock supply to work, the working clock required by the existing high-speed system-on-chip is usually obtained by a low-frequency clock source after frequency multiplication by a phase-locked loop (PLL). The low-frequency clock source Usually it is the system-on-chip internal clock source or an external clock source. [0003] Since the operating frequency of the system on chip is determined in the application, the operating clock output by the PLL needs to be determined. Therefore, for the PLL, the low-frequency input clocks of different frequencies need to be corrected to the input clock frequency valu...

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Problems solved by technology

[0004] However, since the above method needs to configure the frequency divider through software, and when the application of the system on chip is determined, the software program will also be fixed. Therefore, when the external clock source needs to be replaced by another frequency clock source due to some factors In order to ensure the determinism of the operating frequency of the system on chip, the software needs to be modified to conform to the configuration program of the frequency division of the new clock source, which will reduce the work efficiency and increase the complexity of the process, and if the software program is not modified, only The external clock source can be replaced with a clock source of the same frequency, which limits application development

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