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Parameter configuration method, device and system for multi-channel high-speed analog-to-digital conversion chip

A high-speed analog-to-digital conversion, multi-channel technology, applied in the direction of analog-to-digital converter, electrical digital data processing, data processing input/output process, etc., can solve the problem of low efficiency of multi-channel high-speed analog-to-digital conversion chip parameters, and achieve Improve debugging efficiency, stabilize work performance, and solve the effect of low parameter efficiency

Active Publication Date: 2019-05-03
BEIJING INST OF RADIO MEASUREMENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a parameter configuration method, device and system for a multi-channel high-speed analog-to-digital conversion chip, to at least solve the technical problem of low efficiency in the prior art of manually adjusting the parameters of a multi-channel high-speed analog-to-digital conversion chip

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  • Parameter configuration method, device and system for multi-channel high-speed analog-to-digital conversion chip
  • Parameter configuration method, device and system for multi-channel high-speed analog-to-digital conversion chip
  • Parameter configuration method, device and system for multi-channel high-speed analog-to-digital conversion chip

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Embodiment 1

[0018] According to an embodiment of the present invention, a method embodiment of a method for configuring parameters of a multi-channel high-speed analog-to-digital conversion chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a set of computer executable instructions, for example. and, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

[0019] figure 1 It is a parameter configuration method of a multi-channel high-speed analog-to-digital conversion chip according to an embodiment of the present invention, such as figure 1 As shown, the method includes the following steps:

[0020] Step S102, inputting a preset signal to the multi-channel high-speed analog-to-digital conversion chip;

[0021] Step S104, obtaining signal output results of multiple channels of the multi-channel high-speed analog-to-digi...

Embodiment 2

[0073] According to an embodiment of the present invention, a product embodiment of a parameter configuration device for a multi-channel high-speed analog-to-digital conversion chip is provided, Figure 4 It is a parameter configuration device of a multi-channel high-speed analog-to-digital conversion chip according to an embodiment of the present invention, such as Figure 4 As shown, the device includes an input module, a first determination module and a second determination module, wherein the input module is used to input preset signals to the multi-channel high-speed analog-to-digital conversion chip; the first determination module is used to obtain multi-channel high-speed The signal output results of multiple channels of the analog-to-digital conversion chip at different time delay values, determine the best time delay value according to the signal output results; the second determination module is used to determine the best time delay value according to the signal of ea...

Embodiment 3

[0090] According to an embodiment of the present invention, a product embodiment of a parameter configuration system for a multi-channel high-speed analog-to-digital conversion chip is provided, the system includes sequentially connected signal sources, a multi-channel high-speed analog-to-digital conversion chip, a field programmable gate array chip and Digital signal processing chip; wherein, the signal source is used to input sampling data of a preset sampling clock to the multi-channel high-speed analog-to-digital conversion chip; the field programmable gate array chip is used to obtain multiple channels of the multi-channel high-speed analog-to-digital conversion chip in different The output data result at the time delay value; the digital signal processing chip is used to determine the optimal time delay value according to the output signal result; and under the optimal time delay value, determine the DC bias parameters of each channel according to the output data of each ...

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Abstract

The invention discloses a parameter configuration method, device and system for a multi-channel high-speed analog-to-digital conversion chip. The method comprises the following steps: inputting a preset signal to a multi-channel high-speed analog-to-digital conversion chip; acquiring signal output results of a plurality of channels of the multi-channel high-speed analog-to-digital conversion chipat different time delay values, and determining an optimal time delay value according to the signal output results; and under the optimal time delay value, determining a direct current bias parameter,an amplitude adjustment parameter and a phase delay parameter of each channel according to the signal output result of each channel. The technical problem that in the prior art, the efficiency of manually adjusting the parameters of the multi-channel high-speed analog-to-digital conversion chip is low is solved.

Description

technical field [0001] The invention relates to the field of digital circuit design and application, in particular to a parameter configuration method, device and system of a multi-channel high-speed analog-to-digital conversion chip. Background technique [0002] Multi-channel high-speed analog-to-digital conversion chips, such as EV10AQ190A high-speed AD chip, provide 4 independent input channels, which have three modes: single-channel output, dual-channel output, and four-channel output. The maximum input sampling clock frequency is 2.5GHz. After frequency division by the internal clock circuit, the maximum frequency of the sampling clock entering each independent channel is 1.25GHz. When working in single-channel output mode, the data of four channels are spliced ​​into one channel. Data output, its maximum equivalent sampling clock frequency is 5GHz. When multi-channel coherent splicing is performed, the method is to delay the input clock by the corresponding phase, th...

Claims

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Application Information

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IPC IPC(8): G06F3/05H03M1/12
Inventor 郭鑫鹏钟明史永辉易晓丽
Owner BEIJING INST OF RADIO MEASUREMENT
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