A real-time dynamic detection method for a parallel bus fault of a CPU security system

A safety system and bus failure technology, applied in the field of CPU safety system, can solve the problems of no real-time dynamic detection of parallel bus data, address line and transmission function test, etc., and achieve comprehensive test results

Active Publication Date: 2019-05-07
浙江众合科技股份有限公司
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Problems solved by technology

Data, address lines, and transfer function tests wi

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  • A real-time dynamic detection method for a parallel bus fault of a CPU security system
  • A real-time dynamic detection method for a parallel bus fault of a CPU security system
  • A real-time dynamic detection method for a parallel bus fault of a CPU security system

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[0026] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The following description of at least one exemplary embodiment is merely illustrative in nature and in no way taken as limiting the invention, its application or uses. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0028] refer...

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Abstract

The invention discloses a real-time dynamic detection method for a parallel bus fault of a CPU security system. The target device provides two fixed address registers. wherein the fixed address 1 register data is valid through a read signal and a chip selection signal; a positive code of the parallel bus address is triggered and latched in real time; The data of the register of the fixed address 2is written into the inverse code of the parallel bus address of the target equipment, and the CPU security system dynamically judges the correctness of the data transmission process in real time by writing the data of the fixed address 2 and reading out the XOR bit sum of the value of the register and the tested address data and judging whether the value is' 1 'or not. The data transmission process refers to a parallel bus read-write function and data access of target equipment and a CPU safety system, and detection is not limited to possible random interference and device transient failure in the process. Therefore, the bus function signal chip selection, reading and writing, the address and the data line are all tested, and the test is more comprehensive.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a CPU safety system. Background technique [0002] In the CPU security system, in order to ensure the security of system functions, the system needs real-time dynamic detection of each function. Among them, the CPU safety system with parallel data bus usually needs real-time dynamic detection of address lines and data lines, and real-time dynamic detection is required for the correctness of the data transmission process. [0003] The prior art mainly adopts the following three schemes. [0004] Scheme 1: The parallel data bus of the processor subsystem sends (writes or reads) specified address data to the target device, and the target device triggers register latching. The processor then reads the data under the register address. Compare sent and read address data. [0005] Solution 2: When used for equipment PCB detection, the data line and address line of the PCB are dete...

Claims

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Application Information

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IPC IPC(8): G06F11/22
Inventor 邱建平
Owner 浙江众合科技股份有限公司
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