A method and system for reducing ftl address mapping space

Abstract

The present invention relates to a method for reducing the FTL address mapping space and its system; wherein, the method for reducing the FTL address mapping space includes: S1, obtaining mpa and offset according to the logical page address; S2, judging whether the mpa is stored in the cache Hit; S3, judge whether mpa has been written into nand; S4, nomap load operation, return invalid mapping; S5, map load operation; S6, directly find the position mpci of mpa in the cache, combined with offset to find the physical page address gppa; S7, Judging whether it is necessary to modify the logic-to-physical mapping; S8, modifying the mapping table in the cache corresponding to mpci, and marking the mp corresponding to mpci as dirty mp; S9, judging whether to trigger mp to write into the nand condition; S10, changing the dirty mp is written to nand. The present invention adopts the method of dynamically managing the address mapping table in the cache space to replace the method of loading all the address mapping tables in RAM, reduces RAM overhead, and saves hardware costs; realizes the reduction of FTL address mapping table space and SSD under the condition of limited performance impact RAM cost.

Description

Technical field [0001] The present invention relates to the technical field of solid state hard drives, and more particularly to a method of reducing FTL address mapping space and its system. Background technique [0002] The FTL (Flash Translation Layer) algorithm is the core part of the SSD (SOLID State Disk), since Nand does not allow duplicate writing, FTL needs to maintain logic to physical address mapping. At present, if the SSD firmware uses a page mapping, you need to maintain the mapping of all logical pages to physical pages in RAM, while RAM resources in SSD are limited and expensive. If you are 4K as a unit map, it is assumed that one table option in the page map takes up 4B, and the capacity 128G hard disk requires 128m RAM space for storing page mapping tables, which undoubtedly increases the cost of SSD. [0003] The most nature of FTL is the address mapping. The current SSD firmware is currently divided into block mapping, page mapping, mixed mapping; page mapping...

AI Technical Summary

Problems solved by technology

[0003] The most essential work of FTL is address mapping. At present, the common address mapping of SSD firmware is divided into block mapping, page mapping, and mixed mapping; page mapping uses page as the mapping unit, and each logical page address corresponds to a physical page address; in order to pursue more Good random performance (the operating system is very concerned about this), many SSDs will use this mapping method, but because the pages of the flash memory are much more than the blocks of the flash memory, the SSD needs more space to store the mapping table, in order to store this mapping The current mainstream SSD generally stores all the buffer data and mapping table in DRAM. The advantage is that it can quickly find and update the mapping table and has better performance. The disadvantage is that there is one more DRAM, which increases the cost and power consumption; and the price of DRAM is relatively high. , cannot meet the demand

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