Method and system for accelerating Nandboot

Abstract

The invention relates to a method and a system for accelerating Nandboot. The method for accelerating Nandboot comprises the following steps: S1, starting a chip, and NFC and PHY are configured at a low speed; S2, completing the configuration of NandFlash particles in a low-speed state; S3, reading a Header of the boot file in the NandFlash; S4, analyzing the Header, and restarting and initializing the NFC and the PHY into a high speed by using parameters in the Header; S5, reading the rest boot files at a high speed; and S6, loading the boot file and operating the boot file. Through special processing of the boot file, adding corresponding NFC and PHY configuration parameters, when the chip is started, the Nandboot speed is increased by reading the parameters to reconfigure the NFC and the PHY. Meanwhile, due to the fact that the high-speed configuration parameters are written later and can be changed at any time, the situation that the time sequence does not meet the requirement is avoided, and therefore the whole starting speed is increased, time is saved, and the scene with the high chip starting time requirement is met.

Description

Technical field [0001] The invention relates to the technical field of solid state hard disk chips, and more specifically to a method and system for accelerating Nandboot. Background technique [0002] When the chip uses Nandboot to start, the current traditional method uses a constant-speed startup process, that is, use a low-speed NandFlash controller (NFC) and PHY parameters to operate Nandflah. Although the low-speed configuration has lower requirements for PHY parameters, so that the entire chip can have good compatibility with NandFlash, low-speed is more suitable for the initialization of Nand particles, and the later read and write operations on the particles are not dominant. The low-speed first and then high-speed solution is very risky, because the high-speed NFC configuration parameters have high requirements on the chip, and the pre-written parameters may not meet the timing requirements and cause compatibility problems. Therefore, the traditional Nandboot can only u...

AI Technical Summary

Problems solved by technology

Although the low-speed configuration has lower requirements on PHY parameters, etc., so that the entire chip can have good compatibility with NandFlash, but the low-speed configuration is more suitable for the initialization of Nand particles, and the later read and write operations on the particles are not dominant. However, there is a great risk in the solution of low speed first and then high speed, because the high-speed NFC configuration parameters have high requirements on the chip, and the pre-written parameters may not meet the timing requirements, causing compatibility problems, so the traditional Nandboot can only use low speed for the whole process. processing, unable to meet the demand

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