A reconfigurable FFT processor supporting multi-mode configuration

Abstract

A reconfigurable FFT processor supporting multi-mode configuration comprises an on-chip SRAM memory which communicates with an off-chip memory through a data external transmission module; a reconfigurable computing array which comprises a plurality of single-precision floating point adders based on the IEEE-754 standard, the subtracters and the floating point multipliers; an FFT controller which is used for controlling the whole flow of the FFT operation; and the data external transmission module which is used for controlling the data transmission between the processor and the off-chip memory.The beneficial effects are that the processor has the high operation precision, obvious acceleration effect and high utilization rate of hardware resources.

Description

technical field [0001] The invention belongs to the technical field of digital signal processing, in particular to a reconfigurable FFT processor supporting multi-mode configuration. Background technique [0002] In the field of modern communication, especially in wireless communication, FFT is one of the most widely used algorithms. For various application scenarios, or different signals in the same scenario, there are requirements for the same hardware structure to perform FFT operations with different points, and the range of operation points, operation speed and operation accuracy are the three indicators that designers are most concerned about. [0003] In the prior art, the implementation of FFT can be classified into two types of implementation methods: software and hardware. The software method is easy to implement and has high flexibility, but there is a bottleneck in its computing speed, which makes it difficult to meet the requirements of high-speed signal proces...

AI Technical Summary

Problems solved by technology

Using software, it is easy to implement and has high flexibility, but there is a bottleneck in its calculation speed, which makes it difficult to meet the requirements of high-speed signal processing.

Using traditional hardware methods, the special-purpose computing structure represented by ASIC, although it has fast execution speed, low power consumption, and low cost, has a fatal flaw—poor flexibility and scalability, which is mainly reflected in the FFT it supports The number of calculation points is small. Once a higher number of calculation points is required for FFT operations, the entire calculation architecture needs to be redesigned, resulting in a long iterative cycle from design to application.

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