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Detection circuit of semiconductor memory device and semiconductor memory device

A technology for detecting circuits and storage devices, applied in static memory, instruments, etc., to solve problems such as short circuit of reference resistors, distortion, and floating ZQ terminals.

Active Publication Date: 2021-03-23
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the reference resistance connected to the impedance terminal of the DRAM (referred to as the ZQ terminal) is short-circuited to the power supply or ground due to various reasons, or the ZQ terminal is suspended due to an open circuit, ZQ calibration will fail or be distorted.

Method used

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  • Detection circuit of semiconductor memory device and semiconductor memory device
  • Detection circuit of semiconductor memory device and semiconductor memory device
  • Detection circuit of semiconductor memory device and semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] Embodiment 1 of the present invention provides a detection circuit for a semiconductor storage device, such as figure 1 and figure 2 shown, including:

[0055] The resistance unit 100 and the reference resistor 200 are connected in series at the impedance terminal 300 to form a series branch, one end of the series branch is grounded, and the other end of the series branch is connected to a power supply;

[0056] a reference voltage providing unit 400;

[0057] The first comparator 510, the first input terminal 511a of the first comparator is connected to the impedance terminal, and the second input terminal 511b of the first comparator is connected to the first output terminal 410 of the reference voltage supply unit;

[0058] The second comparator 520, the first input terminal 521a of the second comparator is connected to the impedance terminal, and the second input terminal 521b of the second comparator is connected to the second output terminal 420 of the referenc...

Embodiment 2

[0066] Embodiment 2 of the present invention limits the decoding unit and the connection relationship between the decoding unit and the output terminal of the first comparator and the output terminal of the second comparator on the basis of the first embodiment.

[0067] Regarding the circuit of the decoding unit, it can be as follows image 3 as shown,

[0068] The input signal of the first address input terminal 611 of the decoding unit uses X 1 Indicates that the input signal of the second address input terminal 612 is represented by X 2 Indicates that the output signal of the first output terminal 621 is represented by Y 1 Indicates that the output signal of the second output terminal 622 is represented by Y 2 Indicates that the output signal of the third output terminal 623 is represented by Y 3 Indicates that the output signal of the fourth output terminal 623 is represented by Y 4 express;

[0069] The logical expression of the decoding unit satisfies the followin...

Embodiment 3

[0094] Embodiment 3 of the present invention differs from Embodiment 2 in that the logic expressions of the decoding unit are different, such as Figure 4 As shown, the logic expression of the decoding unit 600 in Embodiment 3 of the present invention is: The reasoning process is similar to that in Embodiment 2, and will not be repeated here.

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Abstract

The embodiment of the invention discloses a detection circuit of a semiconductor memory device and the semiconductor memory device. The detection circuit comprises a resistor unit and a reference resistor which are connected in series at an impedance end point to form a series branch; first input ends of a first comparator and a second comparator are connected with the impedance endpoint, and a second input end of the first comparator is connected with a first output end of the reference voltage providing unit; a second input end of the second comparator is connected with a second output end of the reference voltage providing unit; wherein the first output end of the reference voltage providing unit is used for providing a first reference voltage, the second output end of the reference voltage providing unit is used for providing a second reference voltage, and the first reference voltage is smaller than the second reference voltage; and the decoding unit is used for receiving the first comparison signal and the second comparison signal and outputting a signal for judging the state of the impedance end point according to the first comparison signal and the second comparison signal.According to the embodiment of the invention, the state of the impedance endpoint can be quickly judged.

Description

technical field [0001] The invention relates to the technical field of semiconductor storage, in particular to a detection circuit of a semiconductor storage device and the semiconductor storage device. Background technique [0002] In the process of high-speed data transmission, such as data transmission between DRAM and CPU, in order to maintain signal integrity, impedance matching becomes more and more important, so high-precision output ports are required; among them, DRAM is the abbreviation of Dynamic Random Access Memory, The Chinese name is dynamic random access memory, CPU is the abbreviation of Central Processing Unit, and the Chinese name is central processing unit. [0003] However, the output impedance of the output port will vary with the manufacturing process, application environment such as voltage, temperature and other factors. Therefore, DRAM needs to adopt an output port with high precision and adjustable impedance function. Usually, this process of adju...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC