Detection circuit of semiconductor memory device and semiconductor memory device
A technology for detecting circuits and storage devices, applied in static memory, instruments, etc., to solve problems such as short circuit of reference resistors, distortion, and floating ZQ terminals.
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Embodiment 1
[0054] Embodiment 1 of the present invention provides a detection circuit for a semiconductor storage device, such as figure 1 and figure 2 shown, including:
[0055] The resistance unit 100 and the reference resistor 200 are connected in series at the impedance terminal 300 to form a series branch, one end of the series branch is grounded, and the other end of the series branch is connected to a power supply;
[0056] a reference voltage providing unit 400;
[0057] The first comparator 510, the first input terminal 511a of the first comparator is connected to the impedance terminal, and the second input terminal 511b of the first comparator is connected to the first output terminal 410 of the reference voltage supply unit;
[0058] The second comparator 520, the first input terminal 521a of the second comparator is connected to the impedance terminal, and the second input terminal 521b of the second comparator is connected to the second output terminal 420 of the referenc...
Embodiment 2
[0066] Embodiment 2 of the present invention limits the decoding unit and the connection relationship between the decoding unit and the output terminal of the first comparator and the output terminal of the second comparator on the basis of the first embodiment.
[0067] Regarding the circuit of the decoding unit, it can be as follows image 3 as shown,
[0068] The input signal of the first address input terminal 611 of the decoding unit uses X 1 Indicates that the input signal of the second address input terminal 612 is represented by X 2 Indicates that the output signal of the first output terminal 621 is represented by Y 1 Indicates that the output signal of the second output terminal 622 is represented by Y 2 Indicates that the output signal of the third output terminal 623 is represented by Y 3 Indicates that the output signal of the fourth output terminal 623 is represented by Y 4 express;
[0069] The logical expression of the decoding unit satisfies the followin...
Embodiment 3
[0094] Embodiment 3 of the present invention differs from Embodiment 2 in that the logic expressions of the decoding unit are different, such as Figure 4 As shown, the logic expression of the decoding unit 600 in Embodiment 3 of the present invention is: The reasoning process is similar to that in Embodiment 2, and will not be repeated here.
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