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High signal voltage tolerances in single-ended memory interface

An intermediate signal, memory module technology, applied in digital memory information, static memory, information storage and other directions

Pending Publication Date: 2019-07-26
INTEGRATED DEVICE TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The input signal is single-ended

Method used

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  • High signal voltage tolerances in single-ended memory interface
  • High signal voltage tolerances in single-ended memory interface
  • High signal voltage tolerances in single-ended memory interface

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Experimental program
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Embodiment Construction

[0031] Embodiments of the present invention include providing high signal voltage tolerance in a single-ended memory interface that can (i) operate at high supply voltages, (ii) tolerate high signal voltage swings, (iii) sequentially pass through multiple voltage domains Reduce input voltage swing, (iv) provide low latency, (v) provide balanced rise and fall time delays and / or (vi) be implemented as one or more integrated circuits.

[0032] In various embodiments of the invention, a continuous-time linear equalizer (CTLE) circuit operating in the intermediate voltage domain can compensate for multi-drop applications such as channel loss and reflections in memory interface circuitry. Output and input signals generated and received by memory interface circuitry typically exist in the high voltage domain. A data sampling clipping circuit operating in the low voltage domain can differentiate the compensated input signal created by the CTLE circuit. Compared to existing designs, t...

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Abstract

The invention relates to a high signal voltage tolerance in a single-ended memory interface. The device comprises a line termination circuit and a continuous time linear equalizer circuit. The line termination circuit may be configured to generate a data signal in response to an input signal. An input signal is typically present in a first voltage domain. The input signal may be single ended. Thedata signal may be generated in a first voltage domain. The consecutive time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to thereference voltage. The consecutive time linear equalizer circuit is typically operated in a second voltage domain. The first voltage domain may be higher than the second voltage domain.

Description

technical field [0001] The present invention relates generally to signal receivers, and more particularly to methods and / or apparatus for achieving high signal voltage tolerance in single-ended memory interfaces. Background technique [0002] Conventional double data rate fourth generation (DDR4) interfaces specify operation at data rates up to 3.2 gigabits / second. At such high data rates, signal integrity becomes an issue. Continuous time linear equalizer (CTLE) circuits are widely used to compensate channel insertion loss and return loss. The clipping circuit distinguishes the compensated signal. Under various supply conditions, the CTLE output common-mode voltage may become too high for the clipping circuit to properly discriminate. Tests revealed that the receiver failed at high supply voltages. Under large input voltage swing conditions, the receiver setup time results in poor timing margins and poor data eye symmetry. [0003] It would be desirable to achieve high...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/003H03K19/0175
CPCH03K19/00346H03K19/00323H03K19/017509G11C7/1051G11C5/04G11C5/147G11C11/4074G11C11/4093
Inventor 谢毅于跃
Owner INTEGRATED DEVICE TECH INC