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Differential delay circuit, voltage-controlled delay line tuning circuit and chip

A voltage-controlled delay line, differential delay technology, applied in information storage, static memory, digital memory information and other directions, can solve problems such as inability to guarantee, wide tuning range, and inability to achieve ideal results, and achieve stable and safe circuit operation and wide tuning. range, the effect of expanding the tuning range

Inactive Publication Date: 2019-07-30
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the circuit structure, active load control is usually used to expand the tuning range, but simple load adjustment cannot achieve the desired effect, and it cannot guarantee that a wide tuning range can be obtained under different input frequencies.

Method used

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  • Differential delay circuit, voltage-controlled delay line tuning circuit and chip
  • Differential delay circuit, voltage-controlled delay line tuning circuit and chip
  • Differential delay circuit, voltage-controlled delay line tuning circuit and chip

Examples

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Embodiment approach

[0046] According to an implementation manner of the voltage-controlled delay line tuning circuit of the present invention, the control circuit is further configured to: control at least one of the first resistance adjustment unit M2 and the second resistance adjustment unit M5 in the differential delay circuit in response to receiving the enable control signal At least one of the corresponding PMOS transistors is turned on and off. As mentioned above, the first resistance adjustment unit and the second resistance adjustment unit have the same structure and are arranged symmetrically. The differential delay circuit receives the load control signal S[n:0] sent by the control circuit, and controls the on and off of the correspondingly set PMOS transistor according to the load control signal S[n:0], specifically, controls the gate of the PMOS transistor When grounded, the PMOS transistor is in the conduction state, and when the gate of the control PMOS transistor is connected to t...

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PUM

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Abstract

The invention provides a differential delay circuit for a voltage-controlled delay line, a voltage-controlled delay line tuning circuit and a chip. The differential delay circuit for the voltage-controlled delay line comprises a pair of differential input transistors, a voltage signal input unit, a resistance adjusting unit and a cross coupling unit. The resistance adjusting unit and the voltage signal input unit are arranged in parallel, and the resistance adjusting unit is connected with the control circuit and adjusts the load of the resistance adjusting unit according to the load control signal generated by the control circuit so as to adjust the tuning range of the voltage-controlled delay line. According to the technical scheme provided by the embodiment of the invention, the load ofthe differential delay circuit is adjusted by adjusting the conduction and cut-off of the plurality of PMOS tubes in the PMOS tube array, so that the tuning range of the voltage-controlled delay lineis expanded, and the circuit operates more stably and safely.

Description

technical field [0001] The invention relates to a delay circuit structure, in particular to a differential delay circuit, a voltage-controlled delay line tuning circuit and a chip. Background technique [0002] DDR (Double Data Rate, double rate synchronous dynamic random access memory) is SDRAM (Synchronous Dynamic Random Access Memory, synchronous dynamic random access memory) with double transfer rate, its transfer speed is twice the system clock, due to the speed increase, Its transmission performance is better than traditional SDRAM. In the DDR memory system, the voltage-controlled delay line is the main component of the delay line circuit of the delay-locked loop. The voltage-controlled delay line circuit realizes that the analog voltage signal generated by the charge pump controls the output of the delay-locked loop, so as to delay the output of the electrical signal for a period of time. The circuit design of the voltage-controlled delay line mostly uses a pseudo-d...

Claims

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Application Information

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IPC IPC(8): G11C7/10G11C11/4093
CPCG11C7/1057G11C7/1084G11C11/4093
Inventor 李敏娜
Owner CHANGXIN MEMORY TECH INC
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