Standard integrated cell with capacitive decoupling structure

Abstract

The invention discloses a standard integrated cell with a capacitive decoupling structure. The standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standardintegrated cell. The standard integrated cell further includes at capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of priority from French Patent Application No. 1850725 filed January 30, 2018, the contents of which are hereby incorporated by reference in their entirety to the fullest extent permitted by law. technical field [0003] The present invention relates to integrated circuits, and more particularly to standard cells, such as eg input / output cells. Background technique [0004] Standard cells are typically produced using CMOS technology, and are predesigned and optimized for storage, for example, in a standard cell library. Standard cells can have logic functions. Designers of integrated circuits can therefore use these standard cells to locate them and interconnect them according to the architecture of the integrated circuit to be designed. [0005] figure 1 A top view of the logic part LG of the integrated circuit is shown. The logic part LG of an integrated circuit usually compr...

AI Technical Summary

Problems solved by technology

Therefore, capacitive decoupling elements of the gate channel capacitor (channelcap) type produced using MOS technology occupy a dedicated space located on the edge of the logic part LG

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