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LDPC decoding method based on variable node dynamic block update for MLC type NAND-Flash

A technology of LDPC codes and variable nodes, applied in the field of LDPC code decoding, can solve problems such as difficult to meet NAND-Flash error correction performance requirements, and achieve the effects of improving decoding performance, suppressing negative effects, and improving utilization

Active Publication Date: 2019-08-06
SUN YAT SEN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] With the improvement of cell storage density, traditional error correction codes such as Hamming codes and BCH codes have been difficult to meet the error correction performance requirements of NAND-Flash. Since LDPC codes can approach the Shannon limit to the maximum extent, in the case of high code rates It can also achieve good error correction performance without causing too much delay, so it is currently the mainstream error correction code scheme for the reliability of data stored in flash memory technology, and it is also the main research hotspot in the field of high-density storage coding and decoding.

Method used

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  • LDPC decoding method based on variable node dynamic block update for MLC type NAND-Flash
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  • LDPC decoding method based on variable node dynamic block update for MLC type NAND-Flash

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Embodiment

[0065] Such as figure 1 , figure 2 As shown, this embodiment provides an LDPC code decoding method based on variable node dynamic block for MLC type NAND-Flash, including the following steps:

[0066] S1. In the NAND-Flash storage channel, all variable nodes are divided into blocks according to the probability that the voltage of the variable node falls into each area: the variable nodes in the non-overlapping area are divided into Data blocks, and the variable nodes in the overlapping area are divided into Divided into overlapping sub-blocks;

[0067] S2. Continue subdividing each sub-block into a plurality of sub-blocks according to the absolute value of the variable node initial LLR value in each sub-block: continue subdividing the Data block into a data1 sub-block and a data2 sub-block;

[0068] S3. Skip the data1 sub-block, update the variable nodes in the data2 sub-block and the overlap sub-block in sequence, and search out the data1 sub-block, data2 sub-block, and ov...

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Abstract

The invention relates to an LDPC (Low Density Parity Check Code) decoding method based on variable node dynamic block update for an MLC (Multi-Link Control) type NAND-Flash, which comprises the stepsthat S1, in an NAND-Flash storage channel, dividing variable nodes in a non-overlapping region into Data blocks, and dividing the variable nodes in the overlapping region into overlap sub-blocks; S2,continuously subdividing the Data blocks into a plurality of data sub-blocks; s3, skipping a plurality of data sub-blocks, sequentially updating the variable nodes in the remaining data sub-blocks andoverlapping sub-blocks respectively according to the sequence, searching out low-value variable nodes in each data sub-block and overlap sub-block respectively, and updating the low-value variable nodes according to the sequence; s4, judging whether a judgment condition is met or not, if yes, updating variable nodes of the plurality of data sub-blocks skipped in the step S3 in sequence and repeating the step S3, and if not, repeating the step S3; and S5, judging whether the decoding is successful or not, if not, continuing the step S4, and if so, ending. Information generated by updating thereliable nodes is used for driving and updating unreliable nodes, and the utilization rate of iteration updating information is increased.

Description

technical field [0001] The invention relates to the technical field of communication coding, in particular to an LDPC code decoding method for MLC-type NAND-Flash based on dynamic block updating of variable nodes. Background technique [0002] In 1962, Gallager proposed the LDPC (Low Density Parity Check) code for the first time in a paper, and gave the definition, construction method and decoding method of the LDPC code in the paper. The two decoding methods mentioned in the paper are: hard-decision decoding based on bit flipping (BF, Bit Flipping) and soft-decision decoding based on posterior probability (Posteriori Probability), which laid a theoretical foundation for subsequent research , but due to the limitations of computer processing power and storage capacity at that time, LDPC codes did not attract the attention of researchers. Until 1996, MacKay and Neal re-researched LDPC codes on the basis of Gallager's research. The two used randomized construction to construc...

Claims

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Application Information

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IPC IPC(8): H04L1/00H03M13/11G06F11/10
CPCG06F11/1056G06F11/1068H03M13/1105H04L1/005H04L1/0057
Inventor 刘星成郭婷梁硕
Owner SUN YAT SEN UNIV
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