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VR chip control method and system based on PECI bus

A chip control and BMC chip technology, applied in the field of VR chip control methods and systems based on PECI bus, can solve problems such as missing the best time to solve problems, destroying the scene, and consuming power technicians to measure and debug time, so as to improve development Efficiency, the effect of improving efficiency

Inactive Publication Date: 2019-08-13
深圳市国鑫恒宇科技有限公司
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During the development process of the server motherboard, the development and debugging of the VR chip power supply system requires a lot of measurement and debugging time for power supply technicians.
During the stable operation of the server motherboard, if there is a stuck situation, it is necessary to destroy the site, reconnect the oscilloscope or Intel professional debugging tools, and reproduce the problem, often missing the best time to solve the problem

Method used

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  • VR chip control method and system based on PECI bus
  • VR chip control method and system based on PECI bus

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Embodiment Construction

[0031] The present invention will be further described below in conjunction with the description of the drawings and specific embodiments.

[0032] The nouns are explained as follows:

[0033] BMC: Baseboard Management Controller (Baseboard Management Controller). Generally built into the motherboard, it supports the industry-standard IPMI specification. Functions provided by the BMC include: local and remote diagnostics, console support, configuration management, hardware management, and troubleshooting.

[0034] IPMI: (Intelligent Platform Management Interface) Intelligent Platform Management Interface is an open standard hardware management interface specification that defines a specific method for embedded management subsystems to communicate.

[0035] ME: (Intel Management Engine) Intel Management Engine.

[0036] VID: (Voltage Identification) Code provided by the processor to determine the reference output voltage delivered to the processor input pin.

[0037] VR: (Vo...

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PUM

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Abstract

The invention provides a VR chip control method based on a PECI bus. Based on a PECI bus, commands are sent through a BMC to obtain VR chip information, fixed static information is displayed to a userto be looked up, and dynamic information is updated in real time. If output information exceeds the tolerance standard range, an alarm prompt mechanism is triggered, a VID command interface is provided, and debugging is carried out. The invention discloses a VR chip control system based on a PECI bus. The method and the system have beneficial effects that each server can display static and dynamic information of the VR chip through the BMC management interface, all users can look up the static and dynamic information and verify whether the static and dynamic information exceeds tolerance standards or not, debugging can be carried out without an oscilloscope or a Britier professional debugging tool, the development efficiency is improved, and the troubleshooting and problem solving efficiency is improved.

Description

technical field [0001] The invention relates to a VR chip control method, in particular to a PECI bus-based VR chip control method and system. Background technique [0002] Intel processors follow Moore's Law, and the update speed is very fast. The power supply circuit system around the processor is becoming more and more complex. The power supply chip of the peripheral power supply circuit, that is, the VR chip, must also be updated along with the processor. The selection of the VR chip, the design of the peripheral circuit of the VR chip, and the parameter configuration of the VR chip play a decisive role in whether the processor can work stably. The VR chip power supply system needs to be designed by professional power supply technicians, adjust the parameter configuration through the measurement of precision instruments such as oscilloscopes, and adjust the output parameters to the best state to ensure the stable operation of the processor. [0003] The design of the VR...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G06F11/32
CPCG06F11/328G06F13/4072G06F2213/0026
Inventor 赵士亮
Owner 深圳市国鑫恒宇科技有限公司
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