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Demodulation circuit of wireless receiver

A wireless receiver and demodulation circuit technology, applied in the field of demodulation circuits, can solve the problems of increased chip cost and limited performance, and achieve the effects of improving stability and reliability, receiving data stably and reliably, and reducing design costs

Active Publication Date: 2019-09-06
GIANTEC SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But these two methods inevitably increase the cost of the chip, and the performance improvement is very limited

Method used

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  • Demodulation circuit of wireless receiver
  • Demodulation circuit of wireless receiver
  • Demodulation circuit of wireless receiver

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Experimental program
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Embodiment Construction

[0041] based on the following Figure 1 to Figure 10 , specifically explain the preferred embodiment of the present invention.

[0042] Such as figure 1 As shown, the present invention provides a demodulation circuit 900 of a wireless receiver, including:

[0043] The front-stage analog demodulator (RF Receive Demodulator) 950, its input end is connected to the antenna ports ANT1 and ANT2 for receiving signals, and its output end is connected to the digital anti-jamming circuit 960;

[0044] Digital Anti-Disturb Architecture (Digital Anti-Disturb Architecture) 960, its input end is connected to the front-stage analog demodulator 950, and its output end is connected to the rear-stage digital demodulator 970, which is used to realize the anti-interference of the width of the clock edge and the definition of the data boundary. Anti-interference, counting between two consecutive pulses, and extraction of characteristic information displayed by counting between two consecutive pu...

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Abstract

A demodulation circuit of a wireless receiver uses a digital anti-interference circuit to connect a pre-stage analog demodulator and a post-stage digital demodulator, and is used for extracting characteristic information of width interference resistance of a clock edge, interference resistance of a data boundary, counting between two continuous pulses and counting display between the two continuous pulses. According to the invention, the front-stage and back-stage design difficulty is simplified; the stability and reliability of the demodulation circuit can be greatly improved, the design costof the pre-stage analog demodulator and the design cost of the post-stage digital demodulator are reduced, the whole demodulation circuit can tolerate interference from an external magnetic field andan internal analog demodulator, the whole demodulation circuit has high anti-interference capacity, and stable and reliable data receiving is kept.

Description

technical field [0001] The invention relates to a demodulation circuit of a wireless receiver. Background technique [0002] In the complex 13.56MHz wireless communication environment, the wireless smart card conforming to the ISO / IEC15693 protocol adopts the amplitude keying modulation (ASK) method when receiving data in wireless communication, and the pulse position modulation (PulsePosition Modulation) is used for data encoding. The magnetic field environment is relatively complicated, and it is subject to various interferences from card readers, magnetic fields, and multiple cards. Therefore, for the smart card chip, it is required to be able to tolerate a certain degree of interference. [0003] The demodulator of the smart card chip is composed of an analog demodulator and a digital demodulator. Among them, the analog demodulator is located in the front stage, and the digital demodulator is located in the rear stage. Due to the limitation of cost and power consumpti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B1/10H04L27/06
CPCH04B1/10H04L27/06
Inventor 马新元
Owner GIANTEC SEMICON LTD