Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof

Abstract

The invention provides a laminated structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. The laminated structure for the three-dimensional memory comprises sacrificial layers and inter-gate dielectric layers which are alternately arranged up and down in a laminated manner. The laminated structure is internally provided with channel through holes running through the laminated structure along the thickness direction of the laminated structure, the parts of each channel through hole are different in width along the thickness direction of the laminated structure; the thickness of the sacrificial layers is in direct proportion to the width of the channel through hole, and the thickness of the inter-gate dielectric layers is inversely proportional to the width of the channel through hole. The laminated structure for the three-dimensional memory can make up the influence brought about by the inconsistency of the channels through holes formed in the laminated structure and the poor morphology of the channel through holes; in the three-dimensional memory formed based on the laminated structure for the three-dimensional memory, all memory units have the same in programming / erasing speed, the erasing state coupling effect is good, all memory units have good uniformity in performance, the threshold voltage of the three-dimensional memory is narrow, and the performance stability of the three-dimensional memory is good.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. Background technique [0002] In the existing semiconductor process, with the continuous improvement of memory density requirements, the number of stacked structures in the three-dimensional memory is continuously increased, and the aspect ratio of the channel vias (CH) formed in the stacked structures is also increasing. Higher and higher. For channel vias with a high aspect ratio, due to the limitation of the existing etching process, the bottom morphology of the formed channel vias is relatively poor, for example, the morphology of the bottom of the channel vias will be deformed (distortion) Or there are defects such as streaks (striation), and at the same time, the width of the channel vias formed is inconsistent, for ...

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a stacked structure for a three-dimensional memory, a three-dimensional memory and its preparation method. The layer structure, three-dimensional memory and its preparation method are used to solve the problem in the prior art that the memory cells corresponding to the smaller part of the channel via hole width are compared with the memory cells corresponding to the larger part of the channel via hole width. The programming / erasing speed is fast, the memory cells corresponding to the smaller part of the channel via hole have more serious read interference, the erased state coupling effect is poor, and the characteristics of the memory cells in each part of the memory are inconsistent, resulting in the threshold voltage of the three-dimensional memory The distribution is wide, which affects the performance of the three-dimensional memory and other issues

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