Laminated structure used for three-dimensional memory, three-dimensional memory and preparation method thereof

Abstract

The invention provides a laminated structure used for a three-dimensional memory, the three-dimensional memory and a preparation method thereof. The laminated structure comprises sacrificial layers and inter-grid medium layers which are laminated vertically and alternately; a channel through hole running through the laminated structure along the thickness direction of the laminated structure is formed in the laminated structure, and along the thickness direction of the laminated structure, the widths of each part of the channel through hole are different; and the thicknesses of the sacrificiallayers are in direct proportion to the width of the channel through hole. The thicknesses of the sacrificial layers in the laminated structure used for the three-dimensional memory provided by the invention are in direct proportion to the width of the channel through hole, and influences caused by the width non-uniformity of the channel through hole formed in the laminated structure and poor appearance of the channel through hole can be compensated; based on the three-dimensional memory formed by the laminated structure used for the three-dimensional memory, the programming / erasing speeds ofall storage units are the same, the erasing state coupling effect is preferable, the performances of all storage units are preferably uniform, the threshold voltage of the three-dimensional memory isrelatively narrow, and the performance stability of the three-dimensional memory is high.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. Background technique [0002] In the existing semiconductor process, with the continuous improvement of memory density requirements, the number of stacked structures in the three-dimensional memory is continuously increased, and the aspect ratio of the channel vias (CH) formed in the stacked structures is also increasing. Higher and higher. For channel vias with a high aspect ratio, due to the limitation of the existing etching process, the bottom morphology of the formed channel vias is relatively poor, for example, the morphology of the bottom of the channel vias will be deformed (distortion) Or there are defects such as streaks (striation), and at the same time, the width of the channel vias formed is inconsistent, for ...

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Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof, which are used to solve the existing problem of the three-dimensional memory in the prior art corresponding to channel communication. Compared with the memory cells corresponding to the larger portion of the channel via width, the memory cells with a smaller hole width are programmed / erased faster, and the memory cells corresponding to the smaller portion of the channel via hole width are more severely read. The coupling effect of the erased state is poor, and the characteristics of the memory cells in each part of the memory are inconsistent, resulting in a wide distribution of the threshold voltage of the three-dimensional memory, thereby affecting the performance of the three-dimensional memory, etc.

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