Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof

Abstract

The invention provides a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof, including sacrificial layers and inter-gate dielectric layers alternately stacked up and down; For the channel via hole of the layer structure, along the thickness direction of the laminated structure, the width of each part of the channel via hole is different; the thickness of the inter-gate dielectric layer is inversely proportional to the width of the channel via hole. The thickness of the inter-gate dielectric layer in the stacked structure used in the three-dimensional memory of the present invention is inversely proportional to the width of the channel via hole, which can compensate for the inconsistency of the channel via hole width and the shape of the channel via hole formed in the stacked structure. In the three-dimensional memory formed based on the stacked structure of the three-dimensional memory of the present invention, all memory cells have the same programming / erasing speed, the erasing state coupling effect is better, and the performance of all memory cells has Good uniformity, the threshold voltage of the three-dimensional memory is relatively narrow, and the performance stability of the three-dimensional memory is good.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. Background technique [0002] In the existing semiconductor process, with the continuous improvement of memory density requirements, the number of stacked structures in the three-dimensional memory is continuously increased, and the aspect ratio of the channel vias (CH) formed in the stacked structures is also increasing. Higher and higher. For channel vias with a high aspect ratio, due to the limitation of the existing etching process, the morphology of the formed channel vias is relatively poor, for example, the topography of the bottom of the channel vias will be deformed (distortion) or There are defects such as streaks (striation), and at the same time, the width of the channel vias formed is inconsistent, for example...

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Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof, which are used to solve the existing problem of the three-dimensional memory in the prior art corresponding to channel communication. Compared with the memory cells corresponding to the larger portion of the channel via width, the memory cells with a smaller hole width are programmed / erased faster, and the memory cells corresponding to the smaller portion of the channel via hole width are more severely read. The coupling effect of the erased state is poor, and the characteristics of the memory cells in each part of the memory are inconsistent, resulting in a wide distribution of the threshold voltage of the three-dimensional memory, thereby affecting the performance of the three-dimensional memory, etc.

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