Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof

A stacked structure and memory technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of inconsistent characteristics of memory storage units, serious reading interference of storage units, and affecting the performance of three-dimensional memory, etc.

Active Publication Date: 2019-10-25
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof, which are used to solve the existing problem of the three-dimensional memory in the prior art corresponding to channel communication. Compared with the memory cells corresponding to the larger portion of the channel via width, the memory c

Method used

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  • Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof
  • Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof
  • Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof

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Embodiment 1

[0113] see figure 1 , the present invention provides a stacked structure 11 for a three-dimensional memory, the stacked structure 11 for a three-dimensional memory includes sacrificial layers 111 and inter-gate dielectric layers 112 alternately stacked up and down; A channel via hole 14 penetrating through the laminated structure 11 along the thickness direction of the laminated structure 11 is formed. Along the thickness direction of the laminated structure 11, the width of each part of the channel via hole 14 varies. Same; the thickness of the inter-gate dielectric layer 112 is inversely proportional to the width of the channel via hole 14 .

[0114] As an example, the laminated structure 11 can be divided into an upper part and a lower part from top to bottom along the thickness direction of the laminated structure 11, and the ratio of the upper part of the laminated structure 11 to the total thickness of the laminated structure 11 is It can be set according to actual need...

Embodiment 2

[0126] see Figure 11The present invention also provides a stacked structure 12 for a three-dimensional memory, the stacked structure 12 includes gate layers 121 and inter-gate dielectric layers 112 alternately stacked up and down; The thickness direction of the stacked structure 11 runs through the channel via hole 14 of the stacked structure 11, and along the thickness direction of the stacked structure 11, the width of each part of the channel via hole 14 is different; The thickness of the inter-gate dielectric layer 112 is inversely proportional to the width of the channel via 14 .

[0127] As an example, the laminated structure 11 can be divided into an upper part and a lower part from top to bottom along the thickness direction of the laminated structure 11, and the ratio of the upper part of the laminated structure 11 to the total thickness of the laminated structure 11 is It can be set according to actual needs; similarly, the ratio of the lower part of the laminated ...

Embodiment 3

[0139] see Figure 21 , the present invention also provides a method for preparing a three-dimensional memory, the method for preparing a three-dimensional memory includes the following steps:

[0140] 1) Provide a semiconductor substrate;

[0141] 2) forming the stacked structure as described in Embodiment 1 on the semiconductor substrate;

[0142] 3) forming an epitaxial layer at the bottom of the channel via hole;

[0143] 4) forming a functional sidewall on the sidewall of the channel via hole, and forming a channel layer on the surface of the functional sidewall and the upper surface of the epitaxial layer;

[0144] 5) forming a gate gap in the stacked structure;

[0145] 6) removing the sacrificial layer based on the gate gap to form a sacrificial gap; and

[0146] 7) Forming a gate layer in the sacrificial gap.

[0147] In step 1), see Figure 21 Step S1 in and Figure 22 , providing a semiconductor substrate 13 .

[0148] As an example, the semiconductor substr...

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Abstract

The invention provides a laminated structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. The laminated structure comprises a sacrificial layer and an inter-gate dielectric layer which are alternately laminated up and down; a channel through hole penetrating the laminated structure in the thickness direction of the laminated structure is formed in the laminated structure, and the width of each part of the channel through hole is different in the thickness direction of the laminated structure; the thickness of the inter-gate dielectric layer is inversely proportional to the width of the channel through hole. The thickness of the inter-gate dielectric layer in the laminated structure for the three-dimensional memory is inversely proportional tothe width of the channel through hole, so that the influence caused by the inconsistent width of the channel through hole formed in the laminated structure and the poor appearance of the channel through hole can be compensated; in the three-dimensional memory formed by the laminated structure of the three-dimensional memory, the programming/erasing speeds of all memory cells are consistent, the coupling effect in an erasing state is better, the performances of all memory cells have better uniformity, the threshold voltage of the three-dimensional memory is narrower, and the performance stability of the three-dimensional memory is good.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. Background technique [0002] In the existing semiconductor process, with the continuous improvement of memory density requirements, the number of stacked structures in the three-dimensional memory is continuously increased, and the aspect ratio of the channel vias (CH) formed in the stacked structures is also increasing. Higher and higher. For channel vias with a high aspect ratio, due to the limitation of the existing etching process, the morphology of the formed channel vias is relatively poor, for example, the topography of the bottom of the channel vias will be deformed (distortion) or There are defects such as streaks (striation), and at the same time, the width of the channel vias formed is inconsistent, for example...

Claims

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Application Information

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IPC IPC(8): H01L27/11582
CPCH10B43/27H10B41/35H10B43/20H10B43/35
Inventor 王启光周文犀
Owner YANGTZE MEMORY TECH CO LTD
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