Memory cell array peripheral circuit and memory device

Abstract

The embodiment of the invention discloses a memory cell array peripheral circuit and a memory device, the memory cell array comprises a plurality of memory cell planes, and each memory cell plane comprises M local word lines; each global word line in the peripheral circuit corresponds to a plurality of local word lines on each storage unit plane and is in one-to-one correspondence with the global word line voltage selection modules; the local word line voltage selection modules are in one-to-one correspondence with the local word lines; the global word line voltage selection module selects one voltage from the selected voltage and the unselected voltage and outputs the voltage to the input end of the corresponding local word line voltage selection module through the corresponding global word line; and the local word line voltage selection module selects one voltage from the voltage output by the corresponding global word line voltage selection module and the unselected voltage and outputs the selected voltage to the corresponding local word line. Due to the fact that the local word lines share one global word line, the occupied area of the required multiplexer is reduced, and the area of a peripheral circuit can be reduced.

Description

Technical field [0001] This application relates to the field of memory technology, and in particular to a peripheral circuit of a memory cell array and a storage device. Background technique [0002] NAND Flash storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. With the advent of the era of big data, the planar structure of NAND devices has approached the limit of actual expansion. In order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND Flash memory is proposed. [0003] In 3D NAND Flash memory, such as figure 1 As shown, a plurality of memory cell tubes (memory cells) are connected in series via bit lines (BL) to form a memory cell string. The memory cell strings str are arranged in a three-dimensional direction to form a memory cell array. One end is also connected to a page buffer via BL, and different memory cell tubes along the memor...

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Problems solved by technology

[0005] In view of this, the embodiment of the present application provides a memory cell array peripheral circuit and a memory device, which can solve the problem of excessive peripheral circuit area in the prior art

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