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Apparatus and system for in-band dynamic random access memory error correction coding

A memory, memory address technology, applied in memory systems, static memory, response errors, etc., can solve problems such as errors not being detected and corrected

Pending Publication Date: 2019-10-11
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Some non-ECC memories with parity support allow errors to be detected, but not corrected; otherwise, errors are not detected

Method used

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  • Apparatus and system for in-band dynamic random access memory error correction coding
  • Apparatus and system for in-band dynamic random access memory error correction coding
  • Apparatus and system for in-band dynamic random access memory error correction coding

Examples

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Embodiment Construction

[0020] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The disclosed subject matter may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0021] It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. On, connected to or coupled to said other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "dire...

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Abstract

An apparatus and a system for in-band dynamic random access memory error correction coding are disclosed. According to one general aspect, an apparatus may include a memory configured to store both data and metadata, such that for portions of data associated with the metadata, the data and metadata are interleaved such that a unit of metadata succeeds each power of two contiguous units of data. The apparatus may also include a memory manager circuit. The memory management circuit may be configured to receive a data access to the memory, wherein the data access includes a public memory address.The memory management circuit may be configured to determine if the public memory address is associated with metadata. The memory management circuit may be configured to, if so, convert the public memory address to a private memory address. The memory management circuit may be configured to complete the data access at the private memory address.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 649,524, filed March 28, 2018, entitled "In-Band DRAM ECC." The subject matter of this earlier filed application is hereby incorporated by reference. technical field [0002] This specification relates to computer memory management, and more particularly to in-band dynamic random access memory (DRAM) error correction coding (ECC). Background technique [0003] Modern semiconductor memory devices typically use error detection and correction bits to provide a processor or other component with a reliable means of storage. In general, error correcting code memory (ECC memory) is a type of computer data storage that can detect and / or correct the most common types of internal data corruption. ECC memory is used in most computers where data corruption cannot be tolerated under any circumstances (such as for scientific or financial computing). [0004] Ideally, ECC memory creates a memory system ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G06F11/10
CPCG11C29/42G06F11/1008G06F11/108G11C2029/0411G11C29/52G06F2212/1032G06F12/0607G06F2212/7207G06F2212/7201G06F12/0292G06F12/0238G06F11/1048G06F11/1012G06F12/06G06F11/1068G06F2212/608G06F12/0895
Inventor 布莱恩·D·马利塔
Owner SAMSUNG ELECTRONICS CO LTD