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UVM-based large-scale memory read-write verification platform and UVM-based large-scale memory read-write verification method

A verification platform and memory technology, applied in the electronic field, can solve problems such as limited configurable range and insufficient versatility, and achieve the effects of stable design, reduced storage space occupation, and improved simulation speed

Active Publication Date: 2019-10-25
福州数据技术研究院有限公司
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AI Technical Summary

Problems solved by technology

However, the configurable range is limited and the versatility is not enough
(2) Created by the logic designer: The logic designer builds the simulation model by himself according to different project applications, and generally only conducts targeted verification for the logic implementation part, so the built model is highly targeted, but not universal enough

Method used

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  • UVM-based large-scale memory read-write verification platform and UVM-based large-scale memory read-write verification method
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  • UVM-based large-scale memory read-write verification platform and UVM-based large-scale memory read-write verification method

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Embodiment Construction

[0036] Such as Figure 1-6 As shown in one of them, the present invention discloses a large-scale memory read-write verification platform based on UVM, which includes a UVM verification test framework and a design module to be tested, the UVM verification test framework includes a sequence scheduler and a sequence generator, and the sequence generation The controller controls the generation and delivery of stored messages and arranges the sequence of stored messages on the time axis. The sequence scheduler drives the design module to be tested through a driver, and the sequence scheduler performs read and write tests on the design module to be tested through the driver. The design module to be tested will The test feedback information is output to the monitor and the scoreboard in sequence; the UVM verification test framework also includes a virtual storage controller and a virtual storage space, and the virtual storage space is used to initialize the virtual storage space and ...

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Abstract

The invention discloses a UVM-based large-scale memory read-write verification platform and a method thereof. Based on the UVM, the time and the space consumed by the verification platform are balanced by automatically judging dense and sparse storage behaviors of large-scale storage and differentially treating storage target areas, so that the occupied storage space during operation can be reduced, and the simulation speed is increased. The simulation verification platform model which is flexible in configuration, simple in operation and light in weight operation is provided for a large-scalememory read-write design module, and stable design and high-quality output can be guaranteed.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a UVM-based large-scale memory read-write verification platform and a method thereof. Background technique [0002] In the field of field programmable gate array and chip design, it is usually necessary to simulate and verify the read and write logic design of the memory. This work requires a memory read and write verification platform. Especially in recent years, in the process of implementing AI algorithms in field programmable arrays and chips, the data storage scale is large, the data access is intensive, the correlation between data is weak, and the overhead caused by large-scale memory read and write operations is increasing. Therefore, an efficient large-scale memory simulation verification platform is needed to ensure the stable output of the device under test. The existing simulation models that use large-scale memory mainly include the following types: (1) Provided...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/26G06F17/50
CPCG06F11/261G06F30/398
Inventor 刘培汪玉林峰葛广君梁爽
Owner 福州数据技术研究院有限公司
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