Manufacturing method of zeroth interlayer film

Abstract

The invention discloses a manufacturing method of a zeroth interlayer film. The method comprises the steps of: the step 1, forming first gate structures at the surface of a semiconductor substrate, wherein areas between the first gate structures are spacer areas, a side wall is formed, and a contact hole etching stop layer consisting of a nitride film is formed; the step 2, growing a zeroth interlayer film; the step 3, performing first selective chemical mechanical polishing to polish the zeroth interlayer film and stopping on the contact hole etching stop layer on the top surface of the sidewall; the step 4, performing second non-selective chemical mechanical grinding to grind the oxide film and the nitride film simultaneously and stop on the contact hole etching stop layer on the top surface of a polysilicon gate; and the step 5, performing third selective etching to remove the residual contact hole etching stop layer on the top surface of the polysilicon gate. The manufacturing method of the zeroth interlayer film can eliminate the butterfly defect of the zeroth interlayer film and can improve the product yield.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing the zeroth interlayer film. Background technique [0002] In the current advanced logic chip technology, multiple device units are integrated on the same semiconductor substrate wafer. The gate structure of the device unit includes polysilicon gates. The spacing of each polysilicon gate is not exactly the same, but has a variety of spacing values. The space between the polysilicon gates often needs to be filled with the zeroth interlayer film (ILD0). When the growth of the zeroth interlayer film is completed, it will also extend to the top region of the polysilicon gate outside the spacer, and then chemical mechanical polishing (CMP) is required to remove the zeroth interlayer film on the top region of the polysilicon gate outside the spacer and polishing the zeroth interlayer film of the spacer to be level with the top s...

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And if more grinding is done in order to ensure that there is no metal residue, it is easy to grind the

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