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FPGA built-in code version loading method and electronic equipment

An electronic device and version technology, applied in the field of information processing, can solve the problem that the switching speed cannot meet the high-speed requirements of the phased array antenna system, and achieve the effect of improving the update efficiency, reducing the probability of FPGA damage, and improving the applicability

Pending Publication Date: 2019-11-05
CHENGDU T-RAY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] This application provides an FPGA built-in code version loading method and electronic equipment to solve the technical problem in the prior art that the signal channel disconnection control switching speed of the radio frequency chip cannot meet the high-speed requirements of the phased array antenna system

Method used

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  • FPGA built-in code version loading method and electronic equipment
  • FPGA built-in code version loading method and electronic equipment

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Experimental program
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Embodiment 1

[0040] Please refer to figure 1 , Embodiment 1 of the present application provides a method for loading an FPGA built-in code version, including:

[0041] Step 101: After receiving the version loading instruction, the processor determines that the bit version code corresponding to the version loading instruction is the first version code data;

[0042] The version loading instruction may be an instruction input by the user, or an instruction automatically issued by the FPGA to load a built-in code satisfying a certain function, and so on. The bit version code in the embodiment of the present application may refer to the built-in code that satisfies the FPGA to realize a certain function, and is not limited to the version name of the code. Therefore, as long as it is an instruction that can be used to represent a certain function that the FPGA needs to implement, or an instruction that represents the name of the bit version that the FPGA needs to load, it can be used as the ve...

Embodiment 2

[0064] Embodiment 2 of the present application provides an electronic device applied to FPGA, including:

[0065] Housing 201;

[0066] FPGA connection end, in order to connect described FPGA202;

[0067] The storage device connection end is used to connect the storage device 203; it should be noted that the connection method in the embodiment of the present application can be wired or wireless;

[0068] Processor 204, arranged in the housing, connected with the storage device connection end and the FPGA connection end, for after receiving the version loading instruction, determine that the bit version code corresponding to the version loading instruction is first version code data; reading the first version code data from the storage device in a predetermined manner; loading the first version code data into FPGA by the processor.

[0069] Specifically, the processor 204 may be a general-purpose central processing unit (CPU), or an application-specific integrated circuit (En...

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Abstract

The invention discloses an FPGA built-in code version loading method and an electronic device. A plurality of different bit version code data are pre-stored in the storage device, and the processor reads the corresponding bit version code data from the storage device according to requirements and loads the bit version code data into the FPGA, so that a mode of updating built-in software of the FPGA by adopting an external simulator is avoided. The method has the technical effects that the FPGA damage probability is reduced, the updating efficiency of FPGA built-in software is improved, and theapplicability of the FPGA to different systems is improved.

Description

technical field [0001] The invention relates to the technical field of information processing, in particular to an FPGA built-in code version loading method and electronic equipment. Background technique [0002] At present, in the FPGA development system, due to the continuous upgrade and expansion of FPGA functions, in order to adapt to different functional requirements, the built-in code of FPGA also needs to be continuously reprogrammed accordingly. The traditional method for programming and updating the built-in software program of the FPGA is: use the emulator to program the FPGA through the Boundary-scan and JTAG interface of the FPGA. Only one bit version can be stored on-chip. Whenever it is necessary to frequently update and upgrade the FPGA system, it often consumes a lot of manpower, material resources and time costs. At the same time, this method needs to expose the JTAG interface of the FPGA during execution, which is likely to cause physical damage to the FP...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/65G06F8/71
CPCG06F8/65G06F8/71
Inventor 余鹏伍泓屹王金先王伟周鹏唐凯
Owner CHENGDU T-RAY TECH CO LTD