Alignment mark with grating pattern and method for forming same
A technology for aligning marks and devices, applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve problems such as limiting the number of solder balls
Active Publication Date: 2021-04-27
TAIWAN SEMICON MFG CO LTD
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- Description
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Problems solved by technology
Furthermore, with the fixed ball size requirement, the solder balls must have a specific size, which in turn limits the number of solder balls that can be packaged on the die surface
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[0017] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming the first part over or on the second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include between the first part and the second part Embodiments in which additional components may be formed between, so that the first and second components may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed....
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A method of forming a semiconductor device includes: encapsulating a device die in an encapsulation material, forming a first dielectric layer over the device die and the encapsulation material, forming first redistribution lines extending into the first dielectric layer to electrically connected to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution line and the alignment mark, and A second redistribution line extending into the second dielectric layer is formed to be electrically connected to the first redistribution line. Second redistribution lines are formed using alignment marks for alignment. Embodiments of the present invention relate to an alignment mark having a grating pattern and a method for forming the same.
Description
technical field [0001] Embodiments of the present invention relate to an alignment mark having a grating pattern and a method for forming the same. Background technique [0002] As semiconductor technology advances, semiconductor chips / die become smaller and smaller. At the same time, more functions need to be integrated into the semiconductor die. As a result, semiconductor dies need to pack more and more I / O pads into smaller areas, and as a result, the density of I / O pads increases rapidly over time. As a result, packaging of semiconductor dies becomes more difficult, which can adversely affect packaging yield. [0003] Traditional packaging techniques can be divided into two categories. In the first category, the dies on the wafer are packaged before the dies on the wafer are diced. This packaging technology has some advantageous features such as greater throughput and lower cost. Additionally, less underfill or molding compound is required. However, this packaging...
Claims
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IPC IPC(8): H01L21/60H01L23/544
CPCH01L23/544H01L24/43H01L2223/54426H01L21/6835H01L2221/68345H01L2221/68359H01L21/561H01L23/3128H01L25/105H01L2224/18H01L23/5389H01L23/49816H01L25/50H01L25/0657H01L2225/0651H01L2225/06568H01L2225/1035H01L2225/1058H01L2225/1082H01L24/19H01L24/20H01L24/29H01L24/32H01L2224/32225H01L2224/27436H01L2224/83191H01L2224/73267H01L2224/92244H01L2224/04105H01L2224/12105H01L2224/48227H01L24/48H01L2224/97H01L24/97H01L2224/19H01L2224/45099H01L2924/0001H01L2924/00014H01L2224/83H01L2223/544H01L21/78H01L21/76897H01L21/76H01L21/56H01L23/3114H01L23/5383H01L23/5386H01L21/4853H01L21/4857H01L21/568H01L21/565H01L2224/214
Inventor 王之妤朱永祺廖思豪胡毓祥郭宏瑞
Owner TAIWAN SEMICON MFG CO LTD