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Integrated circuit comprising capacitive element, and manufacturing method

A technology of integrated circuits and capacitive elements, which is applied in the field of low-voltage capacitive elements and can solve problems such as poor performance

Pending Publication Date: 2019-11-12
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Conventional technologies for MOS (Metal-Oxide-Silicon) type capacitors provide better performance in terms of surface capacitance values ​​but poorer performance in terms of low voltage variations

Method used

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  • Integrated circuit comprising capacitive element, and manufacturing method
  • Integrated circuit comprising capacitive element, and manufacturing method
  • Integrated circuit comprising capacitive element, and manufacturing method

Examples

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Embodiment Construction

[0035] figure 1 is a cross-sectional view of a capacitive element C of an integrated circuit C1 comprising a first electrode E1 and a second electrode E2 electrically separated by an inter-electrode dielectric therebetween.

[0036] The capacitive element C is located on the semiconductor well PW having the first conductivity type, more specifically, on a region of the well PW called an active region, ie a portion not covered by the lateral isolation region STI.

[0037] In this case the well PW is part of the upper part of the underlying semiconductor substrate, but could obviously be an isolated well of the "triple well" type.

[0038] For example, the first conductivity type is P-type, therefore, the second conductivity type opposite to the first conductivity type is N-type. The opposite case can also be considered.

[0039] A lateral isolation region STI such as a shallow trench isolation type allows the active region adjacent to the well PW to be electrically isolated....

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Abstract

Embodiments of the present application relate to an integrated circuit comprising a capacitive element and a manufacturing method. A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French Patent Application No. 1853778, filed May 2, 2018, the content of which is hereby incorporated by reference in its entirety to the fullest extent permitted by law. technical field [0003] Embodiments and implementations of the present invention relate to integrated circuits, particularly low voltage capacitive elements. Background technique [0004] In fact, components for processing radio-frequency signals of integrated circuits and analog components particularly require capacitors with linear capacitance values ​​for low voltages, typically for voltages close to 0V at their terminals. [0005] For example, between 0.0V and 0.5V, a variation of less than 10% to 15% of the capacitance value is considered acceptable. [0006] Typically, such capacitors are made from the interface of two layers of conductive material separated by, for example, a dielectric layer of MOM (Met...

Claims

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Application Information

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IPC IPC(8): H01L27/11526H01L49/02
CPCH01L28/40H01L28/75H10B41/40H01L29/66181H01L29/94H10B41/42H01L28/60H01L29/0649H01L27/101H01L27/0629H01L27/0805H01L27/0733H10B41/00
Inventor A·马扎基
Owner STMICROELECTRONICS (ROUSSET) SAS