Latch and frequency divider
A technology of latches and logic units, which is applied in the direction of power reduction of electrical components, field effect transistors, logic circuits, etc., can solve the problem of large power consumption, and achieve the effect of reducing power consumption and saving resources
Active Publication Date: 2019-11-19
SPREADTRUM COMM (SHANGHAI) CO LTD
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Problems solved by technology
[0004]However, the high-speed divider by two in the prior art has the problem of high power consumption no matter it is under static working conditions or dynamic working conditions
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[0044] See figure 1 As shown, the high-speed frequency divider by two in the prior art may include latches 101 and 102, wherein the latch 101 and the latch 102 are subsequent units of each other. The frequency of the output signal of the high-speed frequency divider is 1 / 2 of the frequency of the input signal, and it can realize the output of the quadrature frequency division signal with a duty ratio of 25% or 75%.
[0045] figure 2 A schematic circuit structure diagram of a latch in a high-speed frequency divider by two for realizing a frequency-divided signal with a duty cycle of 25% is shown. See figure 2 shown. The latch includes a first logic unit 201 and a second logic unit 202 coupled between a reference power VREF_1 and a reference ground VREF_2.
[0046] The first logic unit 201 has a first clock signal input terminal CLK1, a previous stage clock signal input terminal D and an inverted clock signal output terminal Qn, and the second logic unit has a second clock...
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The invention provides a latch and a frequency divider. The latch comprises a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a control unit, wherein the first logicunit and the second logic unit have the same structure; the third logic unit and the fourth logic unit have the same structure; the first logic unit and the third logic unit are connected in series between a reference power supply and a reference ground wire, and the second logic unit and the fourth logic unit are connected in series between the reference power supply and the reference ground wire; and the control unit is suitable for controlling the current path where the first logic unit and the third logic unit are located or the current path where the second logic unit and the fourth logic unit are located to be disconnected when the latch is in a preset working condition. According to the scheme, the power consumption of the latch of the high-speed binary frequency divider circuit under static and dynamic working conditions can be reduced.
Description
technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a latch and a frequency divider. Background technique [0002] With the development of communication technology, the high-speed frequency divider based on the razavi structure latch has been widely used because of its advantages of high speed and wide bandwidth. [0003] The high-speed frequency divider circuit for frequency division by two is composed of two stages of latches, any one of which is the subsequent unit of the other latch. [0004] However, the high-speed frequency divider by two in the prior art has the problem of high power consumption no matter it is under static working conditions or dynamic working conditions. Contents of the invention [0005] The embodiment of the present invention solves how to reduce the power consumption of the latch of the high-speed divide-by-two circuit. [0006] In order to solve the above problems, an embodiment of the...
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IPC IPC(8): H03K19/00H03K19/094H03K21/00
CPCH03K19/0013H03K19/094H03K21/00
Inventor 赵亮赖玠玮何济柔
Owner SPREADTRUM COMM (SHANGHAI) CO LTD