AES verification device based on UVM verification methodology

A verification methodology and verification device technology are applied in the field of AES verification devices based on UVM verification methodology, and can solve problems such as low reusability, low verification efficiency, and cumbersomeness.

Pending Publication Date: 2019-12-03
广州粒子微电子有限公司
View PDF2 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method has low reusability, low

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AES verification device based on UVM verification methodology
  • AES verification device based on UVM verification methodology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0031] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses an AES verification device based on UVM verification methodology. The device comprises: a sequence generation module, a register model, an adapter, an AHB system agent, an AHBbus interface, an AHB bus input monitoring agent, an AHB bus output monitoring agent, an AES reference module and a scoreboard. The AES is connected with an AHB bus and comprises an AES internal register, and the sequence generation module is configured to generate a randomized test vector sequence. The register model receives the test vector sequence and maps an AES internal register. The adapterconverts the test vector sequence into an AHB sequence which can be identified by the AHB system agent. The AHB system agent comprises an AHB sequence transmitter and an AHB bus driver. AHB bus interface operation information is sent to an AES algorithm model of the AES reference module, and a calculation result of the AES algorithm model is sent to the scoreboard. The AHB bus output monitoring agent outputs the operation result of the AES to the scoreboard, and the scoreboard compares the calculation result of the AES algorithm model with the operation result of the AES to verify the AES.

Description

technical field [0001] The present disclosure relates to the technical field of communication, and in particular to an AES verification device based on UVM verification methodology. Background technique [0002] Moore's Law states that the number of transistors that can be accommodated in an integrated chip will double approximately every 18 months, and the performance will double. With the improvement of semiconductor manufacturing process, the emergence of large-scale system-on-chip SOC and multi-core design, the complexity of ASIC design increases exponentially, which makes verification work a bottleneck in the chip design process. The increase in design complexity urgently requires new technologies and methodologies in functional verification. [0003] AES technology is a symmetric block encryption technology, which uses 128-bit block encryption data and provides higher encryption strength than WEP / TKIPS RC4 algorithm. The encryption table and decryption table of AES a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F15/78G06F11/22G06F11/263H04L9/06
CPCG06F15/7871G06F11/2205G06F11/263H04L9/0631
Inventor 罗灏文
Owner 广州粒子微电子有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap