AES verification device based on UVM verification methodology

Abstract

The invention discloses an AES verification device based on UVM verification methodology. The device comprises: a sequence generation module, a register model, an adapter, an AHB system agent, an AHBbus interface, an AHB bus input monitoring agent, an AHB bus output monitoring agent, an AES reference module and a scoreboard. The AES is connected with an AHB bus and comprises an AES internal register, and the sequence generation module is configured to generate a randomized test vector sequence. The register model receives the test vector sequence and maps an AES internal register. The adapterconverts the test vector sequence into an AHB sequence which can be identified by the AHB system agent. The AHB system agent comprises an AHB sequence transmitter and an AHB bus driver. AHB bus interface operation information is sent to an AES algorithm model of the AES reference module, and a calculation result of the AES algorithm model is sent to the scoreboard. The AHB bus output monitoring agent outputs the operation result of the AES to the scoreboard, and the scoreboard compares the calculation result of the AES algorithm model with the operation result of the AES to verify the AES.

Description

technical field [0001] The present disclosure relates to the technical field of communication, and in particular to an AES verification device based on UVM verification methodology. Background technique [0002] Moore's Law states that the number of transistors that can be accommodated in an integrated chip will double approximately every 18 months, and the performance will double. With the improvement of semiconductor manufacturing process, the emergence of large-scale system-on-chip SOC and multi-core design, the complexity of ASIC design increases exponentially, which makes verification work a bottleneck in the chip design process. The increase in design complexity urgently requires new technologies and methodologies in functional verification. [0003] AES technology is a symmetric block encryption technology, which uses 128-bit block encryption data and provides higher encryption strength than WEP / TKIPS RC4 algorithm. The encryption table and decryption table of AES a...

AI Technical Summary

Problems solved by technology

This method has low reusability, low verification efficiency and cumbersome

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