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High-speed data architecture based on network-on-chip and data transmission method

A technology of high-speed data and architecture, applied in the direction of digital transmission system, transmission system, data exchange network, etc., can solve the problems of global clock synchronization difficulty, ADC sampling rate and resolution can not be improved at the same time, to improve clock synchronization accuracy , Improve data transmission speed, improve the effect of data sampling rate

Active Publication Date: 2019-12-10
GUILIN UNIV OF ELECTRONIC TECH
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Problems solved by technology

However, under the limitation of process conditions, it is impossible to increase the sampling rate and resolution of the ADC at the same time. Most of the existing high-speed data architectures use bus-type time-interleaved sampling technology. When the acquisition nodes need to be expanded, the global clock synchronization will become very difficult

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  • High-speed data architecture based on network-on-chip and data transmission method
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  • High-speed data architecture based on network-on-chip and data transmission method

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Embodiment Construction

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0051] see figure 1 , is a schematic structural diagram of a network-on-chip-based high-speed data architecture provided by the present invention, including an analog-to-digital conversion chip resource node 101, a 10 Gigabit Ethernet resource node 104, a resource network interface 102, a router 105, and a switch 106. There are multiple routers 105 arranged in a matrix, the resource node and the resource network interface 102, the resource network interface 102 and...

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Abstract

The invention discloses a high-speed data system structure based on a network-on-chip and a data transmission method. The high-speed data system structure comprises an analog-to-digital conversion chip resource node, a resource network interface, a router and a 10-gigabit Ethernet resource node; the analog-to-digital conversion chip resource node is used for collecting data of external signals andtransmitting the data to the router through the resource network interface; the router is used for receiving the data and transmitting the data to the next router through a link channel; and the 10-gigabit Ethernet resource node is used for receiving the data sent by the next router and sending the data to the switch. The data transmission speed of the network-on-chip is improved.

Description

technical field [0001] The invention relates to the technical field of on-chip networks, in particular to a high-speed data architecture and data transmission method based on on-chip networks. Background technique [0002] With the development of science and technology, data acquisition has higher and higher requirements on performance indicators such as sampling rate and resolution of an analog-to-digital converter chip (Analog-to-Digital Converter, ADC). However, under the limitation of process conditions, it is impossible to increase the sampling rate and resolution of the ADC at the same time. Most of the existing high-speed data architectures use bus-type time-interleaved sampling technology. When the acquisition nodes need to be expanded, the global clock synchronization will become very difficult. Contents of the invention [0003] The purpose of the present invention is to provide a high-speed data system structure and a data transmission method based on an on-chi...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06H04L12/933
CPCH04J3/0635H04L49/109
Inventor 许川佩廖加锋范兴茂牛军浩胡聪
Owner GUILIN UNIV OF ELECTRONIC TECH
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