Variable format, variable sparsity matrix multiplication instruction

Abstract

Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M x K), (K x N), and (M x N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: routeeach row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M x N) processing array, and route each column of the specified B matrix, staggering subsequent columns,into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

Description

technical field

[0001] The field of the invention relates generally to computer processor architecture and, in particular, to variable format, variable sparse matrix multiply instructions. Background technique

[0002] Machine learning architectures such as deep neural networks have been applied in domains including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics, and drug design. Deep learning is a class of machine learning algorithms. Maximizing the flexibility and cost-efficiency of deep learning algorithms and computations can help meet the needs of deep learning processors, such as those performing deep learning in data centers.

[0003] Matrix multiplication is a critical performance / power limitation of many algorithms, including machine learning. Some traditional matrix multiplication methods are specialized, such as they lack the flexibility to support various data fo...

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