A kind of integrated cmos detector and preparation technology
A detector and circuit technology, applied in the field of integrated CMOS detectors and fabrication processes, can solve problems such as incompatibility of Si-based CMOS circuit processes, and achieve the effects of easy implementation, mature growth process and low cost
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Embodiment 1
[0033] A CMOS single-chip detector in this embodiment includes a silicon substrate 1 and an insulating layer 2 from bottom to top. A CMOS circuit 3 is formed on the insulating layer 2. The CMOS circuit 3 is composed of a symmetrical NMOS circuit and a PMOS circuit. A lead-out electrode 4 is formed on the circuit and the PMOS circuit, and a pair of interdigital electrodes 5 are formed in the area between the NMOS circuit and the PMOS circuit, including a left interdigital electrode and a right interdigital electrode, and the interdigital electrodes 5 are located on the insulating layer 2. On the upper surface, the extraction electrode 4 is interconnected with the interdigital electrode 5, and the top of the interdigital electrode 5 is covered with Al x Ga y In 2-x-y o 3 active layer 6.
[0034] The preparation process of the above-mentioned CMOS single-chip detector comprises the following steps:
[0035] (1) Select plane (110) silicon as the substrate, with a thickness of ...
Embodiment 2
[0041] This embodiment is an integrated CMOS wide-band detector array, which includes a silicon substrate 1 and an insulating layer 2 from bottom to top, a CMOS circuit 3 is formed on the insulating layer 2, an extraction electrode 4 is formed on the CMOS circuit 3, and the CMOS circuit 3 The interdigital electrode array 5 is formed in the area between, and the interdigital electrode array 5 is located on the upper surface of the insulating layer 2. The interdigital electrode array 5 is a 2*2 square matrix module, and the lead-out electrodes 4 are interconnected with the interdigital electrodes. The electrode array 5 is divided into four regions, and the upper parts of the four regions are covered with Al x Ga y In 2-x-y o 3 active layer 6.
[0042] By adjusting the composition of Al, Ga, In elements, and Al x Ga y In 2-x-y o 3 The growth position of the material can realize the detection of different wavelengths of light in different regions, and realize the detection ...
Embodiment 3
[0055] In this embodiment, a preparation process of an integrated CMOS broadband detector array comprises the following steps:
[0056] (1) Select plane (110) silicon as the substrate, with a thickness of about 400 μm. A silicon oxide insulating layer is formed on the surface of the silicon substrate, and photoresist is spin-coated on the insulating layer, and then photolithography, thermal diffusion and other processes are performed. CMOS circuit and lead-out electrodes;
[0057] (2) Perform photolithography on the structure obtained in step (1), cover part of the CMOS circuit area with photoresist, and expose the designed 4 Al x Ga y In 2-x-y o 3 4 of the active layer material growth regions;
[0058] (3) Make an array of interdigitated electrodes on the exposed area of the structure obtained in step (2). The interdigitated electrodes are located on the upper surface of the insulating layer. The array of interdigitated electrodes is a 2*2 square matrix module, and Ni / A...
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