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Apparatuses and method for reducing sense amplifier leakage current during active power-down

A technology for sensing amplifiers and devices, applied in the field of memory, which can solve the problem of memory consumption of extra power

Active Publication Date: 2019-12-24
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Leakage current may cause memory to consume additional power

Method used

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  • Apparatuses and method for reducing sense amplifier leakage current during active power-down
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  • Apparatuses and method for reducing sense amplifier leakage current during active power-down

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Embodiment Construction

[0013] Hereinafter, various embodiments of the present invention will be explained in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which show, by way of illustration, certain aspects and embodiments of the invention. The detailed description contains sufficient detail to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0014] figure 1 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 may include a clock input circuit 105, an internal...

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Abstract

Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifiercomprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node ofthe sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.

Description

technical field [0001] The present disclosure relates generally to memory, and more particularly, to apparatus and methods for reducing sense amplifier leakage current during active power down. Background technique [0002] High data reliability, high-speed memory access, and reduced chip size are desirable features of semiconductor memories. In recent years, efforts have been made to further increase the speed of memory while reducing power consumption. In some applications, memory can be placed in a powered down or standby state to reduce power consumption for a period of time. Memory operations can be suspended while the memory is in a powered-off or standby state. In some examples, to reduce transitions to normal operation, the memory suspends portions of the memory in a high voltage state. One side effect of suspending some circuits in a higher voltage state may include unintended leakage current through portions of the circuit. Leakage current may cause the memory ...

Claims

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Application Information

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IPC IPC(8): G11C7/06G11C7/08G11C5/14G11C8/08G11C8/14
CPCG11C7/06G11C7/08G11C5/148G11C8/08G11C8/14G11C11/4091G11C11/4094G11C11/4076G11C7/065G11C16/225G11C8/12G11C2207/005G11C2207/002G11C7/062G11C8/10
Inventor C·卡瓦姆拉
Owner MICRON TECH INC