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Method for forming fin field effect transistor and semiconductor device

A fin field effect, semiconductor technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as increasing the complexity of processing and manufacturing ICs

Active Publication Date: 2019-12-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This shrinking also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances

Method used

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  • Method for forming fin field effect transistor and semiconductor device
  • Method for forming fin field effect transistor and semiconductor device
  • Method for forming fin field effect transistor and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0067] Example 1 is a method for forming a fin field effect transistor comprising: forming a dummy gate electrode layer over a semiconductor region; forming a mask strip over the dummy gate electrode layer; using the mask strip performing a first etching process to pattern the upper portion of the dummy gate electrode layer using as a first etch mask, wherein the remaining portion of the upper portion of the dummy gate electrode layer forms a dummy gate electrode the upper part of the dummy gate electrode; forming a protective layer on the sidewall of the upper part of the dummy gate electrode; performing a second etching process on the lower part of the dummy gate electrode layer to form the dummy gate electrode a lower portion, wherein the protective layer and the masking strip are used in combination as a second etch mask; and replacing the dummy gate electrode and underlying dummy gate dielectric with a replacement gate stack.

example 2

[0068] Example 2 includes the method of Example 1, wherein a lower portion of the dummy gate electrode layer is etched in a process comprising: etching the lower portion until the dummy gate electrode is exposed layer; and trimming the lower portion of the dummy gate electrode to have a tapered profile.

example 3

[0069] Example 3 includes the method of example 1, wherein the sidewalls of the upper portion of the dummy gate electrode are substantially straight, and the sidewalls of the lower portion of the dummy gate electrode are smaller than the dummy gate electrode. The upper portion of the gate electrode is more inclined.

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Abstract

The invention relates to a method for forming a fin field effect transistor and a semiconductor device. The method includes the steps: forming a dummy gate electrode layer over a semiconductor region,forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.

Description

technical field [0001] The present disclosure generally relates to methods and semiconductor devices for forming FinFETs. Background technique [0002] Technological advances in integrated circuit (IC) materials and design have produced several generations of ICs, where each generation has smaller and more complex circuits than previous generations. During IC evolution, functional density (eg, the number of interconnected devices per chip area) typically increases while geometry size decreases. This downscaling process often provides benefits by increasing production efficiency and reducing associated costs. [0003] This scaling has also increased the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. For example, Fin Field Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structure of the FinFET and the method of manufacturing the Fi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/66545H01L29/785H01L21/32137H01L21/32139H01L29/4236H01L29/41791H01L29/7855H01L29/7831H01L21/823431H01L21/0337H01L21/31111H01L21/762
Inventor 林志翰高魁佑张铭庆杨建伦陈昭成章勋明
Owner TAIWAN SEMICON MFG CO LTD