Fault-tolerant structure and fault-tolerant method for redundant silicon through hole in three-dimensional integrated circuit chip

Abstract

The invention relates to a fault-tolerant structure and a fault-tolerant method for a redundant silicon through hole in a three-dimensional integrated circuit chip, and aims to carry out fault tolerance of a defective TSVs by reconstructing a redundant structure so as to enable a chip to return to normal work. The invention discloses a dual redundancy fault-tolerant structure. The method specifically comprises steps that a TSV array is dynamically divided into a plurality of TSV cluster units according to the size of data bit width, the TSV cluster units comprise signal TSV cluster units and redundant TSV cluster units, and a certain proportion of redundant TSV structures are arranged in each signal TSV cluster unit, that is, scattered redundant TSV fault-tolerant structures and aggregatedredundant TSV fault-tolerant structures exist in the TSV array. The dual-redundancy fault-tolerant structure can be reconstructed according to the data bit width, has relatively high flexibility, canrealize fault tolerance of TSV defects appearing separately and dispersedly, and can also realize fault tolerance of TSV cluster defects, so the fault tolerance capability of the three-dimensional integrated circuit chip is greatly improved, and reliability of the chip is further improved.

Description

technical field [0001] The invention belongs to the fault-tolerant structure and method of redundant through-silicon holes in three-dimensional packaging, and specifically relates to the fault-tolerant layout and method of reconfigurable double redundant structure of through-silicon holes. Background technique [0002] With the continuous improvement of integrated circuit integration, the characteristic size of circuit components is gradually approaching its physical limit, and the problems of traditional chip integration technology have gradually become prominent. The three-dimensional integration technology based on silicon vias is considered to be "more than Moore". "The key technology. [0003] TSV (Through Silicon Via) is the through-silicon via technology, which is the core technology to realize the vertical electrical interconnection of three-dimensional system-in-package. This technology manufactures through holes on the silicon substrate of the integrated circuit c...

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Problems solved by technology

In addition, electromigration in interconnect lines can also cause voids in TSVs or RDLs, thereby increasing via resistance, causing signal delays, and ultimately may cause data path failures

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