Semiconductor device including fin-fet

Abstract

A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source / drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source / drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of thegate structure, and the source / drain regions, and contact plugs formed to pass through the etch stop layer to contact the source / drain regions. The source / drain regions have main growth portions in contact with upper surfaces of the active fins.

Description

technical field [0001] Devices and methods relate to semiconductor devices including fin field effect transistors (fin-FETs) and methods of manufacturing the same. Background technique [0002] According to the demand for high integration of semiconductor devices, it becomes more difficult to form a plurality of contact plugs in a limited space. Contact plugs are used to provide electrical connection between the lower patterns and the upper lines. [0003] When the lower pattern is excessively recessed in the process of forming the contact plug, a parasitic capacitance is generated between the gate electrode and the contact plug, and thus a current delay may occur. Contents of the invention [0004] Example embodiments of inventive concepts are directed to providing semiconductor devices with reduced generation of parasitic capacitance and improved operating characteristics. [0005] According to example embodiments, there is provided a semiconductor device including: an...

AI Technical Summary

Problems solved by technology

[0003] When the lower pattern is excessively recessed in the process of forming the contact plug, a parasitic capacitance is generated between the gate electrode and the contact plug, and thus current delay may occur

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