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A Method for Detecting Etching Damage on the Sidewall of a Channel Hole in a Dual Stack Structure

A technology of sidewall etching and stacking structure, which is applied in the direction of semiconductor/solid-state device testing/measurement, semiconductor devices, electrical components, etc., can solve the problems of not meeting 128 layers and increasing the difficulty of defect detection, so as to ensure simplicity and efficiency, The effect of improving usability

Active Publication Date: 2022-04-15
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, as the number of superimposed layers increases, the difficulty of defect detection also increases accordingly. The existing detection methods can no longer meet the defect detection requirements of 128 layers or more than 128 layers.

Method used

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  • A Method for Detecting Etching Damage on the Sidewall of a Channel Hole in a Dual Stack Structure
  • A Method for Detecting Etching Damage on the Sidewall of a Channel Hole in a Dual Stack Structure
  • A Method for Detecting Etching Damage on the Sidewall of a Channel Hole in a Dual Stack Structure

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Embodiment 1

[0067] Embodiment 1 of the present invention provides a method for detecting etch damage on the sidewall of a channel hole in a dual stack structure, such as image 3 shown, including:

[0068] In step 202, an auxiliary channel hole structure is etched; wherein, the deviation between the depth of the auxiliary channel hole and the thickness of the stack structure in the upper stack structure is within a preset range.

[0069] Wherein, the function of generating the auxiliary channel hole structure is to help remove the upper channel structure and the upper stack structure, so it is named as the auxiliary channel hole structure. In the implementation process, the auxiliary channel hole structure has multiple options, including:

[0070] Method 1, front-gate self-alignment structure lithography; method 2, back-gate self-alignment structure lithography; method 3, grid line gap; method 4, gate alignment lithography of customized graphics. The first three of the above four method...

Embodiment 2

[0094] Figure 5-Figure 16 It shows an implementation method according to Embodiment 1 of the present invention, and an example implementation process in a typical dual-stack structure 3D memory processing process using the method in Embodiment 1 as a means. In the embodiment of the present invention, the relevant method steps as shown in Embodiment 1 will be shown, and necessary expansion constraints will be performed based on the characteristics of the embodiment of the present invention to realize the environment. It should be noted that the embodiment of the present invention is a more detailed description in order to better demonstrate the implementation of some implementations in Embodiment 1 in specific scenarios. Therefore, it should not be used as a limit to the scope of protection available in the present invention shrink basis. In the embodiment of the present invention, deep hole punching etching is called SONO punching process, and the memory film is described as...

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Abstract

The invention relates to the technical field of semiconductors, and provides a method for detecting etching damage on the side wall of a channel hole in a double stack structure. Including etching out the auxiliary channel hole structure; wherein, the depth of the auxiliary channel hole and the thickness deviation of the stack structure in the upper stack structure are within a preset range; through the auxiliary channel hole structure, etching away the An upper stack structure above the stack structure, exposing the storage film in the lower channel structure available for detection; wherein the lower channel structure is located in the lower stack structure; and detecting the storage film in the lower channel structure sidewall profile. The present invention selects the key steps that affect the structural integrity of the sidewall of the channel hole, and designs a set that can not only remove the upper channel structure to expose the storage film in the lower channel structure that can be detected, but also maintain the entire The process does not damage the storage film in the lower channel structure, making it possible to detect the etching damage on the side wall of the channel hole in the double stack structure.

Description

【Technical field】 [0001] The invention relates to the technical field of semiconductors, in particular to a method for detecting etching damage on side walls of channel holes in a double stack structure. 【Background technique】 [0002] The more layers of 3D NAND superimposed, the more memory cells can be obtained, but the more layers, the more difficult it is to etch Channel Hole Etch Through (abbreviated as CH ET), so the double stack ( The dual deck) process was developed, which uses two CH ETs to reduce the difficulty of one CH ET. At the same time, as the number of superimposed layers increases, the difficulty of defect detection also increases accordingly. The existing detection methods can no longer meet the defect detection requirements of 128 layers or more than 128 layers. [0003] In view of this, it is an urgent problem to be solved in this technical field to overcome the defects in the prior art. 【Content of invention】 [0004] The technical problem to be sol...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L27/11524H01L27/11556H01L27/1157H01L27/11582H10B41/27H10B41/35H10B43/27H10B43/35
CPCH01L22/12H10B41/35H10B41/27H10B43/35H10B43/27
Inventor 卢峰王恩博高晶
Owner YANGTZE MEMORY TECH CO LTD