Method for manufacturing integrated circuit structure

Abstract

The embodiment of the invention relates to a method for manufacturing an integrated circuit structure. The method includes the steps of: forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Description

technical field [0001] Embodiments of the present invention generally relate to semiconductor devices, and more particularly to field effect transistors such as planar field effect transistors or 3D fin field effect transistors. Background technique [0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation of integrated circuits. In the evolution of integrated circuits, functional density (eg, the number of interconnect devices per chip area) generally increases as geometric dimensions (eg, the smallest component or circuit that a process can produce) shrink. A shrinking process is often beneficial for increasing throughput and reducing associated costs. However, scaling also increases the process complexity of handling and forming integrated circuits....

AI Technical Summary

Problems solved by technology

However, shrinking dimensions also increase the process complexity of handling and forming integrated circuits

[0003] For example, as feature sizes shrink, the process of forming interlayer dielectric layers on source / drain structures in integrated circuit devices often detrimentally damages the structure and performance of other portions of the same integrated circuit device, such as Designed to protect nearby gate spacers of the metal gate structure

While some approaches to reducing these injuries have been employed, they do not fit all needs

Images