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An Embedded Ron Optimized Layout Method for FPGA Hardware Backdoor Detection

A layout method and backdoor technology, applied in geometric CAD, CAD circuit design, etc., can solve the problems of high RON overhead and low hardware backdoor detection rate, and achieve the effects of cost control and good backdoor detection accuracy

Active Publication Date: 2021-03-30
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned deficiencies in the prior art, an embedded RON optimization layout method for FPGA hardware backdoor detection provided by the present invention solves the problems of large RON overhead and low hardware backdoor detection rate

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  • An Embedded Ron Optimized Layout Method for FPGA Hardware Backdoor Detection
  • An Embedded Ron Optimized Layout Method for FPGA Hardware Backdoor Detection
  • An Embedded Ron Optimized Layout Method for FPGA Hardware Backdoor Detection

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Embodiment Construction

[0055] The specific embodiments of the present invention are described below so that those skilled in the art can understand the present invention, but it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes Within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are included in the protection list.

[0056] Such as figure 1 Shown, a kind of embedded RON optimized layout method for FPGA hardware backdoor detection is characterized in that, comprises the following steps:

[0057] S1. Measure the coverage radius of the RO in the RON of the original circuit. Such as figure 2 As shown, the specific steps are:

[0058] S11. Place an RO on the FPGA so that there are no other circuits around it, measure the reference freque...

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Abstract

The invention discloses an embedded RON optimized layout method for FPGA hardware backdoor detection. The present invention can obtain the layout of a ring oscillator network, thereby providing the number of ring oscillators suitable for backdoor detection, so that the overhead of the on-chip integrated ring oscillator network is controlled, and at the same time, for hardware whose scale is within the set threshold Backdoor, the present invention has a good detection accuracy rate of backdoor.

Description

technical field [0001] The invention relates to the technical field of hardware security, in particular to an embedded RON optimized layout method for FPGA hardware backdoor detection. Background technique [0002] In recent years, the security issues of cyberspace have been paid more and more attention, especially the hardware security. Hardware backdoor is one of the most effective means of hardware attack. Such an attack can exist in different stages of the hardware circuit life cycle. By modifying the RTL code and netlist of the hardware circuit, malicious functions can be added. If there is a situation, there will be consequences such as information leakage and denial of service. The hardware backdoor is carefully designed by the attacker, usually difficult to activate and small in scale, and can evade traditional circuit fault testing. Therefore, research on hardware backdoor detection is very important. [0003] A hardware backdoor detection method based on the Ring...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/34G06F30/18
Inventor 王坚张海龙李桓杨鍊陈哲郭世泽
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA