Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor structure and manufacturing process thereof

A manufacturing process and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., and can solve problems such as low trap density

Pending Publication Date: 2020-01-10
YANGTZE MEMORY TECH CO LTD
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present application is to provide a semiconductor structure and its manufacturing process, to solve the problem that the density of traps in the charge trapping layer in the semiconductor device in the prior art is small

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure and manufacturing process thereof
  • Semiconductor structure and manufacturing process thereof
  • Semiconductor structure and manufacturing process thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0094] The semiconductor structure in this embodiment is a 3D NAND memory, and its specific manufacturing process includes:

[0095] providing a substrate 10 of monocrystalline silicon;

[0096] The first insulating dielectric layer 20 and the sacrificial layer 30 are alternately deposited on the substrate 10 to form a preliminary stack structure, thereby forming figure 1 In the shown structure, wherein the first insulating dielectric layer 20 is formed in contact with the substrate 10, the first insulating dielectric layer 20 is a silicon oxide layer, and the sacrificial layer 30 is a silicon nitride layer;

[0097] Etching and removing parts of each of the above-mentioned first insulating dielectric layers 20, parts of each of the above-mentioned sacrificial layers 30, and part of the above-mentioned substrate 10, so that part of the above-mentioned substrate 10 is exposed, forming the following: figure 2 channel hole 11 shown;

[0098]An epitaxial layer 40 of monocrystal...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a semiconductor structure and a manufacturing process thereof. The manufacturing process of the semiconductor structure comprises the following steps of: forming a substrate structure comprising a channel hole, forming a preliminary charge trapping layer in the channel hole, and performing predetermined processing on the preliminary charge trapping layer such that the preliminary charge trapping layer forms a charge trapping layer, the trap density of the charge trapping layer being greater than the trap density of the preliminary charge trapping layer. According to theabove manufacturing method, the preliminary charge trapping layer is formed in the channel, then the preliminary charge trapping layer is subjected to predetermined processing, and a part of materialsin the preliminary charge trapping layer form traps, so that the number of the traps in the formed charge trapping layer is greater than the number of the traps in the preliminary charge trapping layer. According to the manufacturing method, the number of the traps in the charge trapping layer is large, the problem that the number of the traps in the charge trapping layer in the prior art is small is solved, a memory window of the device is ensured to be relatively large, and the device is ensured to have good performance.

Description

technical field [0001] The present application relates to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing process thereof. Background technique [0002] In the prior art, many are usually charge trap type memories, that is, their structures include a charge trapping layer, and the charge trapping layer is often formed by depositing complex Si-N-O materials. [0003] At present, the density of traps in the charge trapping layer is relatively small, so that the memory window of the memory is small, and the performance including reliability of the memory is poor. [0004] The above information disclosed in the Background section is only to enhance the understanding of the background of the technology described herein, therefore, the Background may contain certain information which is not formed in the country for those skilled in the art. known prior art. Contents of the invention [0005] The main purpose of the present appl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/792H01L21/336H01L27/11563
CPCH01L29/792H01L29/66833H10B43/00
Inventor 欧阳颖洁夏志良苏睿王启光
Owner YANGTZE MEMORY TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products