Controllable random fault injection method applied to simulation verification of processor chip

Abstract

The invention relates to a controllable random fault injection method applied to simulation verification of a processor chip. The controllable random fault injection method comprises the following steps of defining a fault injection structure body; finding a design signal path and a name of fault injection according to a design scheme and a design code of the chip, and associating the design signal path and the name with variables in a fault injection environment through a binding mode supported by a simulator; monitoring and acquiring a current exit instruction number, and acquiring a recorded current fault injection number when the exit instruction number is in the fault injection instruction number interval; obtaining a data bit width size, obtaining two different random numbers r0 andr1 by using a pseudo random number generation method, wherein the value ranges of the random numbers r0 and r1 are between 0 and size-1; and selecting a data bit or a signal bit for fault injection byadopting random numbers r0 and r1 according to different error generation conditions. According to the invention, the controllability, randomness and expandability of fault processing flow verification are enhanced.

Description

technical field [0001] The invention relates to the technical field of processor chip simulation verification, in particular to a controllable random fault injection method applied to processor chip simulation verification. Background technique [0002] With the continuous expansion of processor chip design scale and the continuous improvement of design complexity, the correctness verification of processor chips has become increasingly complex and difficult. The fault handling process is an important guarantee for the reliability of the processor, and its correctness verification is crucial. Fault injection in the simulation verification stage can analyze the fault handling process and reliability of the chip in the design stage, thus speeding up the design process and reducing design costs. [0003] In traditional processor chip simulation verification, the correctness verification of faults is generally carried out by forcing signals or modifying specific designs. The me...

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Problems solved by technology

[0004] However, methods of forcing signals and modifying specific designs perform poorly in terms of scalability, controllability, and randomness because they can only operate with specific stimuli and can only be generated at specific times and fixed signal bits. It is impossible to control the timing of errors, and it is also difficult to find design errors hidden at the boundary conditions of the fault handling process

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