An interconnect structure and method for preparing the same

Abstract

An interconnect structure disclosed in an embodiment of the invention includes a substrate; a first insulating layer disposed over the substrate, wherein the first insulating layer has a plurality ofvia holes filled with a first conductive material; a second insulating layer disposed over the first insulating layer, wherein the second insulating layer has a plurality of trenches filled with a second conductive material; a first mask layer disposed between the first insulating layer and the second insulating layer, wherein the first mask layer has a plurality of openings connecting the plurality of via holes and the plurality of trenches; and wherein the plurality of via holes are self-aligned with the plurality of trenches. One of the advantages of the interconnect structure is that preparation processes can be reduced.

Description

[0001] This application is a divisional application of an invention patent application titled "An Inner Wire Structure and Its Preparation Method" with an application date of July 18, 2014 and an application number of 201410344842.9. technical field [0002] The present invention relates to an interconnection structure and a preparation method thereof, especially to an interconnection structure and a preparation method thereof, which has a high process margin. Background technique [0003] The semiconductor manufacturing process usually requires high aspect ratio tungsten contacts of copper back end process (Backt-End-of Line) electrical connection front end process (Front End-of Line). After the semiconductor component is prepared, the interconnection is to electrically connect the semiconductor component and the wire, wherein the interconnection includes a wire part and an intermediate window part. The interposer portion is generally composed of tungsten, and the depositio...

AI Technical Summary

Problems solved by technology

Under-etching often occurs due to difficult etch control, and high aspect ratio tungsten contacts are increasingly difficult to fabricate as electronic components continue to shrink in size

In addition, alignment margins between finely spaced copper traces and tungsten vias continue to shrink, leading to an increased risk of short circuits

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